CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.1 Address Map
Table 3-4. Address Map (1 of 5)
Default
Register
Setting (Hex)
Address
(Hex)
Block
Acronym
R/W
Description
000
080
081
082
083
001
003
DID
R
Device Identification
28
00
00
00
00
00
—
FCR
MIR
MIE
TEST
CR0
IRR
R/W
R
Framer Control Register
Master Interrupt Request
Master Interrupt Enable
Test Configuration
R/W
R/W
R/W
R
Primary Control Register
Interrupt Request Register
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
014
015
016
017
018
019
01A
020
021
ISR7
ISR6
ISR5
ISR4
ISR3
ISR2
ISR1
ISR0
IER7
R
Alarm 1 Interrupt Status
—
—
—
—
—
—
—
00
00
00
00
00
00
00
00
00
—
—
—
—
00
3C
00
—
—
R
Alarm 2 Interrupt Status
R
Error Interrupt Status
R
Counter Overflow Interrupt Status
Timer Interrupt Status
R
R
Data Link 1 Interrupt Status
Data Link 2 Interrupt Status
Pattern Interrupt Status
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Alarm 1 Interrupt Enable Register
Alarm 2 Interrupt Enable Register
Error Interrupt Enable Register
Count Overflow Interrupt Enable Register
Timer Interrupt Enable Register
Data Link 1 Interrupt Enable Register
Data Link 2 Interrupt Enable Register
Pattern Interrupt Enable Register
Loopback Configuration Register
External Data Link Channel
External Data Link Bit
IER6
IER5
IER4
IER3
IER2
IER1
IER0
LOOP
DL3_TS
DL3_BIT
FSTAT
PIO
Offline Framer Status
R/W
R/W
R/W
R/W
R/W
Programmable Input/Output
Programmable Output Enable
Clock Input Mux
POE
CMUX
RAC
Receive Alarm Configuration
Receive Line Code Status
RSTAT
100054E
Conexant
3-3