CX25870/871
Appendix E HDTV Output Mode
Flicker-Free Video Encoder with Ultrascale Technology E.4 Interface Timing between the HDTV Source Device (Master)
Table E-2. CX25870 Register Settings for 24-bit YPrPb Multiplexed In—HDTV YPBPR Out
ATSC Resolution
CX25870
Register
Address
1080i
720p
480p
Explanation
0xD6
0C
0C
0C
OUT_MODE [1:0] field set to 11=DAC Mode to turn on HDTV Outputs.
Video[0-3] is HDTV Output Mode. HDTV_EN bit must be set as well.
Video[0] = HD PR, Video[1] = HD Y, Video[2] = HD PB
0x2E
AB***
09
AA***
09
AD***
08
HDTV_EN set. RGB2YPRPB off. RASTER_SEL[1:0] field adjusted for each ATSC resolution.
HD_SYNC_EDGE set for 480p resolution only.
For EIA770.3 compliance, the trilevel sync has been disabled on both the PR and PB outputs by
setting the RPR_SYNC_DIS(bit 5) and BPB_SYNC_DIS(bit 3) bits.
0x32
DRVS[1:0] = 00 for 3.3V interfacing. Should be adjusted to nonzero value for low voltage interface.
IN_MODE[3] = 1 = input format is Alternate 24bit YPRPB multiplexed
SETUP_HOLD_ADJ bit is bit 4.
CSC_SEL bit set for hi-frequency ATSC resolutions only.
0x3C
0x3E
0x40
0xC4
80
80
80
01
80
80
80
01
80
80
80
01
MCOMPY stays the same for 480p/720p/1080i in, Y/PR/PB out.
MCOMPU stays the same for 480p/720p/1080i in, Y/PR/PB out.
MCOMPV stays the same for 480p/720p/1080i in, Y/PR/PB out.
State of EN_OUT varies according to interface used with master device. Hex value of 01 for this
register corresponds to Pseudo-Master without a BLANK* interface.
0xC6
0xCE
84
24
84
24
84
24
State of EN_BLANKO & EN_DOT varies according to interface used with master device. Hex value of
80 for this register corresponds to Pseudo-Master without a BLANK* interface.
IN_MODE[2:0] = [1]100 - input format is Alternate 24bit YPRPB multiplexed
Adjust this register as necessary to route Y PR PB out from the CX25870's 4 DACs
OUT_MUXD[1:0]= 00 =Video[0] = PR {Disabled from DACDISD=1}
OUT_MUXC[1:0]= 10 =Video[2] = PB
OUT_MUXB[1:0]= 01 =Video[1] = Y
OUT_MUXA[1:0]= 00 =Video[0] = PR
0xA0
0x9E
0x9C
0xBA
21
00
00
28
21*
00**
00**
28
8C
00
00
28
PLL_INT[5:0] = 21 for 720p @ 74.25 MHz
*PLL_INT[5:0] = 20 for 720p @ 74.16 MHz
PLL_FRACT[15:8] = 00 for 720p @ 74.25 MHz
**PLL_FRACT[15:8] = F5 for 720p @ 74.16 MHz
PLL_FRACT[7:0] = 00 for 720p @ 74.25 MHz
**PLL_FRACT[7:0] = C3 for 720p @ 74.16 MHz
SLAVER set. Interface is slave timing (pseudo-master or slave)
HSYNC* & VSYNC* sent to CX25870.
DACD disabled. PR transmitted from DACA, Y transmitted from DACB, and PB transmitted from
DACC
WAIT state
= 75 ms
Yes
C6
Yes
C6
Yes
C6
Ready encoder for timing reset operation. 75 ms = many factors of safety.
0x6C
Set TIMING_RESET bit. Cleared automatically.
NOTE(S):
(*) = If graphics controller is character based with 8 pixel clocks/character, PLL_INT should be modified to generate a 74.16000 MHz CLKO and
CLKI frequency.
(**) = If graphics controller is character based with 8 pixel clocks/character, PLL_FRACT should be modified to generate a 74.16000 MHz CLKO
and CLKI frequency.
(***) = Conversion from YPrpb digital input to HDTV RGB Out not possible with CX25870/871.
100381B
Conexant
E-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
