Appendix E HDTV Output Mode
CX25870/871
E.4 Interface Timing between the HDTV Source Device (Master) and CX25870/ CX25871(Timing Slave)
Flicker-FreeVideo
In the default format, the HSYNC* signal is active low and must always be
received as an input in HDTV Output Mode. Its function is to allow the graphics
controller to tell the encoder when the start of a line occurs. Check the timing
diagrams that appear later in this section for proper HSYNC* timing.
In the default format, the VSYNC* signal is active low and must always be
received as an input in HDTV Output Mode. Its function is to allow the graphics
controller to tell the encoder when the start of a frame occurs. Check the timing
diagrams that appear later in this section for proper VSYNC* timing.
By default, the clock output signal will be transmitted via the CLKO port.
Therefore, the CX25870/871 will be in Pseudo-Master interface. To switch into
Slave interface, the user must reset the EN_OUT bit to turn off CLKO.
Table E-2 summarizes the default Pseudo-Master HDTV interface.
Table E-3. Default State of CX25870/871 Immediately After Switch into HDTV Output Mode
Input Signals
State of the CX25870/871
CLKO
BLANK*
HSYNC*
VSYNC*
State of Encoder in HDTV Output Mode
Digital RGB—Analog HD RGB or
Digital YPRPB—Analog HD YPBPR
Optional
H
H
Active
DAC Conversion
Start of a New Line
Start of a New Frame
Optional
Optional
L
L
H
L
Active
Active
The timing diagrams found at the end of this Appendix (Figures E-5 through
E-9) must be replicated with actual timing by the MPEG2 Decoder or Display
Processor for the encoder to provide correct HDTV analog RGB or analog
YPBPR component video outputs.
E-8
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
