Appendix E HDTV Output Mode
CX25870/871
E.4 Interface Timing between the HDTV Source Device (Master) and CX25870/ CX25871(Timing Slave)
Flicker-FreeVideo
Table E-1. CX25870 Register Settings for Alternate 24-bit RGB Multiplexed In—HDTV YPBPR Out and HDTV RGB Out
ATSC Resolution
CX25870
Register
Address
1080i
720p
480p
Explanation
0xD6
0C
0C
0C
OUT_MODE [1:0] field set to 11=DAC Mode to turn on HDTV outputs.
Video[0-3] is HDTV Output Mode. HDTV_EN bit must be set as well.
Video[0] = HD R or PR, Video[1] = HD G or Y, Video[2] = HD B or PB
0x2E
C3
C2
C5
HDTV_EN set. RGB2YPRPB set. RASTER_SEL[1:0] field adjusted for each ATSC resolution.
HD_SYNC_EDGE set for 480p resolution only.
For RGB out, RGB2YPRPB bit must be 0 so this register will be 83 / 82 / and 85.
For EIA770.3 compliance, disable the trilevel sync on both the PR and PB outputs by setting
the RPR_SYNC_DIS(bit 5) and BPB_SYNC_DIS(bit 3) bits.
0x32
01
01
00
SETUP_HOLD_ADJ bit is bit 4.
CSC_SEL bit set for hi-frequency ATSC resolutions only.
0x3C
0x3E
80
45
80
45
80
48
MCOMPY stays the same for 480p/720p/1080i in, Y/PR/PB out. or RGB out.
MCOMPU must be changed for 480p and 720p/1080i in, Y/PR/PB out.
MCOMPU must be changed to 80hex for 480p/720p/1080i in, RGB out.
0x40
0xC4
0xC6
51
01
80
51
01
80
5B
01
80
MCOMPV must be changed for 480p and 720p/1080i in, Y/PR/PB out.
MCOMPV must be changed to 80hex for 480p/720p/1080i in, RGB out.
State of EN_OUT varies according to interface used with master device. Hex value of 01 for
this register corresponds to Pseudo-Master without a BLANK* interface.
State of EN_BLANKO & EN_DOT varies
according to interface used with master device. Hex value of 80 for this register corresponds
to Pseudo-Master without a BLANK* interface.
IN_MODE[2:0] = 000 - defines input format as 24-bit RGB multiplexed.
0xCE
24
24
24
Adjust this register as necessary to route Y/PR/PB out from the CX25870's 4 DACs
OUT_MUXD[1:0]= 00 =Video[0] = PR = R {Disabled from DACDISD=1}
OUT_MUXC[1:0]= 10 =Video[2] = PB = B
OUT_MUXB[1:0]= 01 =Video[1] = Y = G
OUT_MUXA[1:0]= 00 =Video[0] = PR = R
0xA0
0x9E
0x9C
0xBA
21
00
00
28
21*
00**
00**
28
8C
00
00
28
PLL_INT[5:0] = 21 for 720p @ 74.25 MHz
*PLL_INT[5:0] = 20 for 720p @ 74.16 MHz
PLL_FRACT[15:8] = 00 for 720p @ 74.25 MHz
**PLL_FRACT[15:8] = F5 for 720p @ 74.16 MHz
PLL_FRACT[7:0] = 00 for 720p @ 74.25 MHz
**PLL_FRACT[7:0] = C3 for 720p @ 74.16 MHz
SLAVER set. Interface is slave timing (pseudo-master or slave)
HSYNC*/VSYNC* sent to CX25870.
DACD disabled. PR/Y/PB transmitted from DACA/DACB/DACC
WAIT state =
75 ms.
Yes
C6
Yes
C6
Yes
C6
Ready encoder for timing reset operation. 75 ms = many factors of safety.
0x6C
Set TIMING_RESET bit. Cleared automatically.
(*) = If graphics controller is character based with 8 pixel clocks/character, PLL_INT should be modified to generate a 74.16000 MHz. CLKO and
CLKI frequency.
(**) = If graphics controller is character based with 8 pixel clocks/character, PLL_FRACT should be modified to generate a 74.16000 MHz. CLKO
and CLKI frequency.
E-6
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
