Appendix E HDTV Output Mode
CX25870/871
E.3 Interface Bit Functionality in HDTV Output Mode:
Flicker-Free Video Encoder with Ultrascale Technology
E.3 Interface Bit Functionality in HDTV Output
Mode:
When the CX25870 is transmitting High-Definition Outputs, several interface
bits behave differently than their operation while broadcasting standard-definition
television. These bits and their technical functionality are summarized in the
following list:
•
The BLANK* pin must be an input regardless of the slave or
pseudo-master interface. If the blank function is not enabled with the
BLANK* pin, then the BLANK* pin (#38) should be tied high
permanently.
•
The EN_BLANKO bit has no effect because the BLANK* signal MUST
be an input. The same rule holds for VGA(R/G/B) – DAC Output
operation.
•
•
The EN_DOT bit has no effect. This bit is related to the standard flicker
filter.
The FLD_MODE[1:0] bit field has no effect. For 1080i or any other
HD-related interlaced input, VSYNC*'s leading edge must be received
within 5 clock cycles of the middle of the total line length. For 1080i, this
means the VSYNC* leading edge must be received on any clock period
between the (2200 / 2) 5 clocks = 1095th and 1106th clock pulse.
The polarity reversing bits (HSYNCI, VSYNCI, and BLANKI) perform
the same operations as they do with standard definition outputs.
•
E-4
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
