CX25870/871
Appendix E HDTV Output Mode
Flicker-Free Video Encoder with Ultrascale Technology E.4 Interface Timing between the HDTV Source Device (Master)
E.4 Interface Timing between the HDTV Source
Device (Master) and CX25870/ CX25871(Timing
Slave)
While in HDTV Output Mode, the CX25870/871 encoder should receive
interface signals from the MPEG2 decoder or display processor. The interface
signals that should be shared between the two devices are the HSYNC*,
VSYNC*, BLANK*, CLKI, and Pixel Data lines (P[23:0]). The BLANK* signal
is optional. This signal is only necessary if the data master cannot transmit the
digital codes representing the BLANK levels to the CX25870/871. To reiterate,
the codes for the digital blanking levels of the R, G, B inputs are equal to 00 hex.
The digital codes for blanking change to 10 hex for the R, G, and B pixel inputs if
conversion to offset analog RGB component video outputs is desired. Finally, the
values for digital Y must be 10 hex and for Pr and Pb, digital samples have to
equal 80 hex for the BLANK period for Component Video Out (YPBPR). CLKO
will only be necessary if Pseudo-Master is used as the chosen interface.
To switch the CX25870/871 encoder into HDTV Output mode, the serial
master must program both the OUT_MODE[1:0] bits to 11(DAC Mode) and set
the HDTV_EN bit to 1(bit 7 of the HDTV Register). Immediately after these and
all other steps listed in Table E-1 and Table E-2, the encoder will be set up to
properly generate a set of HDTV Outputs so long as the synchronization, clock,
and data signals are transmitted in accordance with the timing diagrams found at
the back of Appendix E by the master device.
100381B
Conexant
E-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
