Bt8370/8375/8376
5.0 Electrical/Mechanical Specifications
5.5 MPU Interface Timing
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-12. Intel Synchronous Read Cycle
MCLK
1
ALE
2
9
A[8]
AD[7:0]
RD*
Address
3
7
Address
Read Data
4
8
5
6
WR*
CS*
Table 5-15. Intel Synchronous Read Cycle
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
9
15
5
—
—
—
—
—
—
(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
ALE low to RD* and CS* both low
10
5
RD*, CS*, WR* setup to MCLK high (Start RD cycle)
RD*, CS*, WR* hold after MCLK high
Start RD* cycle to AD[7:0] valid
5
10
—
0
RD* or CS* high to AD[7:0] invalid/three-state
End RD cycle to next ALE high
25
0
—
NOTE(S):
(1) Parameter 7 equals 40 ns or 1/2 MCLK + 17 ns, whichever is greater.
N8370DSE
Conexant
5-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
