5.0 Electrical/Mechanical Specifications
5.5 MPU Interface Timing
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-11. Motorola Synchronous Write Cycle
MCLK
1
11
AS*
2
12
A[8:0]
DTACK*
CS*
Address
3
4
5
6
R/W*
9
10
DS*
7
AD[7:0]
Write Data
8
Table 5-14. Motorola Synchronous Write Cycle
Symbol
Parameter
AS* high pulse width
Minimum
Maximum
Units
1
2
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8:0] Address setup to AS* low
A[8:0] Address hold after AS* low
AS* and CS* low to DTACK* low
AS* or CS* high to DTACK* high
CS* and R/W* low to DS* low
AD[7:0] setup to DS* low
5
—
3
10
—
4
0
15
5
0
10
6
10
—
7
0
—
8
AD[7:0] hold after DS* low
DS* setup to MCLK high
15
—
9
5
—
10
11
12
DS* hold after MCLK high
10
—
—
1 / MCLK + 15
—
DS* sampled low to data latch (internal)
DS* sampled low to AS* high
1/2 MCLK + 15
5-14
Conexant
N8370DSE