Bt8370/8375/8376
5.0 Electrical/Mechanical Specifications
5.5 MPU Interface Timing
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-10. Motorola Synchronous Read Cycle
MCLK
1
AS*
9
2
A[8:0]
CS*
Address
3
5
4
DTACK*
R/W*
6
DS*
7
8
AD[7:0]
Read Data
Table 5-13. Motorola Synchronous Read Cycle
Symbol
Parameter
AS* high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
9
15
5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8:0] Address setup to AS* low
A[8:0] Address hold after AS* low
AS* and CS* low to DTACK* low
AS* or CS* high to DTACK* high
AS*, DS*, CS*, R/W* setup to MCLK high
DS* sampled low to AD[7:0] valid
CS* or DS* high to AD[7:0] invalid/three-state
MCLK high to AS* high
—
10
0
—
15
0
10
15
—
0
—
0.5/MCLK +20
25
1/MCLK + 12
—
N8370DSE
Conexant
5-13