5.0 Electrical/Mechanical Specifications
5.5 MPU Interface Timing
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-13. Intel Synchronous Write Cycle
MCLK
1
8
ALE
2
A[8]
AD[7:0]
WR*
Address
3
6
Address
Write Data
7
RD*
4
5
CS*
Table 5-16. Intel Synchronous Write Timing
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
15
—
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
5
—
10
—
WR*,RD*,CS* setup to MCLK high (start WR cycle)
WR*,RD*,CS* hold after MCLK high
5
10
—
—
1/MCLK–10
—
Start WR* cycle to AD[7:0] input data valid
AD[7:0] input data hold after Start WR cycle
Start WR cycle to next ALE high
—
1 / MCLK + 9
1 / MCLK + 10
—
5-16
Conexant
N8370DSE