Bt8370/8375/8376
5.0 Electrical/Mechanical Specifications
5.5 MPU Interface Timing
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-8. Intel Asynchronous Read Cycle
MOTO* = 1, SYNCMD = 0, CLKMD = 0
1
ALE
2
9
A[8]
AD[7:0]
RD*
Address
3
Address
Read Data
4
7
6
WR*
5
8
CS*
Table 5-11. Intel Asynchronous Read Cycle
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
9
15
5
—
—
—
—
—
80
15
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
ALE low to RD* and CS* both low
10
0
WR* high setup to RD* and CS* both low
RD* and CS* both low to AD[7:0] valid
0
—
0
RD* or CS* high to AD[7:0] invalid/three-state
WR* high hold after RD* or CS* high
RD* or CS* high to next ALE
0
0
N8370DSE
Conexant
5-11