5.0 Electrical/Mechanical Specifications
5.5 MPU Interface Timing
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-9. Intel Asynchronous Write Cycle
1
9
ALE
2
A[8]
AD[7:0]
WR*
Address
3
6
Address
Write Data
7
5
RD*
4
8
CS*
Table 5-12. Intel Asynchronous Write Cycle
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
9
15
5
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
CS*, RD* setup to WR* low
10
0
WR* pulse width low
38
0
AD[7:0] input data setup to WR* or CS* high
AD[7:0] input data hold after WR* or CS* high
RD* hold after WR* or CS* high
15
0
End write cycle to next ALE high
55
5-12
Conexant
N8370DSE