Bt8370/8375/8376
5.0 Electrical/Mechanical Specifications
5.6 System Bus Interface (SBI) Timing
Fully Integrated T1/E1 Framer and Line Interface
5.6 System Bus Interface (SBI) Timing
Figure 5-14. SBI Timing - 1536K Mode
Transmit
TSBCKI
Receive
RSBCKI
(4)
RSYNCO(1)
RSYNCI
TSYNCO(1)
TSYNCI
Offset = 008 (TS1, Bit1)(3)
RSYNCO
RSYNCI
TSYNCO
TSYNCI
Offset = 018 (3)
RSYNCO
RSYNCI(1)
TSYNCO
TSYNCI(1)
Offset = 0C7(3)
TS24
TS1
TS2
4
TS3
(4)
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
5 6 7 8 1 2 3 4
RPCMO
RSIGO(6)
RINDO(2)
SIGFRZ
TPCMI
TSIG24
TSIG1
TSIG2
TSIGI(5)
TINDO(2)
A B C D A B C D A B C D A B C D A B C D A B C D
RSBCKI
RSYNCO
RSYNCI
RSYNCO
RSYNCI
TSBCKI
TSYNCO
TSYNCI
TSYNCO
TSYNCI
(4)
Offset = 008(3)
)
(7
Offset = 018 (3)
NOTE(S):
1. TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offset.
2. RINDO/TINDO programmed high or low on a per-time slot basis (SBCn; addr 0E0-0FF).
3. Multiple offset values shown for illustration, refer to OFFSET controls (addr 0D2-0D3, 0D5-0D6).
4. Rising edge outputs and falling edge inputs shown. Refer to Figure 5-19 for other edge combinations.
5. Transmit ABCD signalling on TSIGI is sampled only during low nibble.
6. Received ABCD signalling on RSIGO is repeated in both high and low nibbles.
7. X2CLK control bit located in SBI_CR (addr 0D0).
N8370DSE
Conexant
5-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
