4-Level FSK Modem Data Pump
Page 22 of 50
MX929B PRELIMINARY INFORMATION
4.5.2.19 TSID: Transmit Station ID
This task takes three ID bytes from the Data Block Buffer, calculates and appends the 6-bit CRC0 checksum,
translates the result to 4-level symbols (with FEC) and transmits the resulting 22 symbols preceded and
followed by 'S' symbols.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.20 RESET: Stop any current action
This task takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem
may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should
be used after V is applied first to set the modem into a known state.
DD
Note: Due to delays in the RRC filter, it will take several symbol times for any change caused by RESET to
appear at the TXOUT pin.
4.5.2.21 Task Timing
The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation.
Task
Time
(symbol times)
t
t
Modem in idle state. Time from writing first task to application of first Any
transmit bit to Tx RRC filter
1 to 2
1
Time from application of first symbol of the task to the Tx RRC
T24S
5
6
2
filter until BFREE goes to a logic ‘1’
TSID
THB/TIB/TLB
T4S
16
0
t
t
Time to transmit all symbols of the task
T24S/TSID
THB/TIB/TLB
T4S
24
69
4
18
17
52
3
3
Max time allowed from BFREE going to a logic '1' (high) for next
task (and data) to be written to modem
T24S
4
TSID
THB/TIB/TLB
T4S
t
5
t
6
t
7
Time to receive all symbols of task
SFS
25 (minimum)
SFP
48 (minimum)
RSID
RHB/RILB
R4S
23
69
4
21
21
15
51
3
Maximum time between first symbol of task entering the de-
interleave
SFS
SFP
circuit and the task being written to modem
RSID
RHB/RILB
R4S
Maximum time from the last bit of the task entering the de interleave Any
1
circuit to BFREE going to a logic '1' (high)
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