4-Level FSK Modem Data Pump
Page 24 of 50
MX929B PRELIMINARY INFORMATION
4.5.3 Control Register
This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock
extraction, signal level measurement circuits, and the Frame Sync pattern recognition tolerance to inexact
matches.
Control Register
7 6 5 4 3 2 1 0
CKDIV
FSTOL
LEVRES
PLLBW
4.5.3.1 Control Register B7, B6: CKDIV - Clock Division Ratio
These bits control a frequency divider driven from the clock signal present at the XTAL pin, therefore
determining the nominal symbol rate. Because each symbol represents two bits, bit rates are 2x the symbol
rates. The table below shows how symbol rates of 2400/4800/9600 symbols/sec (4800/9600/19200bps) may
be obtained from common Xtal frequencies:
Xtal Frequency (MHz)
2.4576
4.9152
9.8304
B7
B6
Division Ratio:
Symbol Rate (symbols/sec) / Bit Rate (bps)
Xtal Frequency/Symbol Rate
0
0
1
1
0
1
0
1
512
4800/9600
2400/4800
9600/19200
4800/9600
2400/4800
1024
2048
4096
9600/19200
4800/9600
2400/4800
Note: Device operation is not guaranteed below 2400 symbols/sec (4800bps) or above 9600
symbols/sec (19200bps).
4.5.3.2 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches
These two bits have no effect in transmit mode. In receive mode, they define the maximum number of
mismatches allowed during a search for the Frame Sync pattern:
B5 B4 Mismatches allowed
0
0
1
1
0
1
0
1
0
2
4
6
Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol
'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received
symbol value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for
normal use.
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