4-Level FSK Modem Data Pump
Page 18 of 50
MX929B PRELIMINARY INFORMATION
4.5.2.6 Command Register B2, B1, B0: TASK
Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are initiated
when the µC writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL'
code.
The µC should not write a task (other than NULL or RESET) to the Command Register or write to or read from
the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit
data from the Data Buffer, formatting it as required. The µC should therefore wait until the BFREE (Buffer
Free) bit of the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the
desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte
number 0 of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for
eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting
data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave
Buffer.
Once all of the data has been transferred from the Data Block Buffer, the modem will set the BFREE and
IRQ bits of the Status Register to '1', (causing the chip IRQ output to go low if the IRQEN bit of the Mode
Register has been set to '1') to tell the µC that it may write new data and the next task to the modem.
This lets the µC write the next task and its associated data to the modem while the modem is still transmitting
the data from its previous task.
Data from µC to Block Buffer
Task 1 data
Task 2 data
Task from µC to Command
Register
BFREE Bit of Status Register
IRQ Bit of Status Register
IRQ Output (IRQEN = '1')
TXOUT Signal
from Task 1
from Task 2
Figure 9: Transmit Task Overlapping
When the modem is in receive mode, the µC should wait until the BFREE bit of the Status Register is '1', then
write the desired task to the Command Register.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE bit of the Status Register to '0'.
Wait until enough received symbols are in the De-interleave Buffer.
Decode them as needed and transfer the resulting binary data to the Data Block Buffer
Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the IRQ output
to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the µC that it may read from the
Data Block Buffer and write the next task to the modem. If more than 1 byte is contained in the buffer,
byte number 0 of the data will be read out first.
In this way, the µC can read data and write a new task to the modem while the received symbols needed for
this new task are being received and stored in the De-interleave Buffer.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480171.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CMLMICRO [ CML MICROCIRCUITS ]
