4-Level FSK Modem Data Pump
Page 20 of 50
MX929B PRELIMINARY INFORMATION
4.5.2.9 RHB: Read Header Block
This task causes the modem to read the next 69 symbols as a 'Header' Block. It will strip out the 'S' symbols
then de-interleave and decode the remaining 66 symbols, placing the resulting 10 data bytes and the 2
received CRC1 bytes into the Data Block Buffer and, when the task is complete, setting the BFREE and IRQ
bits of the Status Register to '1'to indicate that the µC may read the data from the Data Block Buffer and write
the next task to the modem's Command Register.
The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1
checksum bytes.
As each of the three 'S' symbols of a block is received, the SVAL bits of the Status Register will be updated
and the SRDY bit set to '1'. (If the SSIEN bit of the Mode Register is '1', then the Status Register IRQ bit will
also be set to '1'.) Note that when the third 'S' symbol is received, the SRDY bit will be set to '1' coincidentally
with the BFREE bit also being set to '1'.
4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block
This task causes the modem to read the next 69 symbols as an 'Intermediate' or 'Last' block. (The µC can tell
from the 'Header' block how many blocks are in the frame and therefore when to expect the 'Last' block).
In each case, it will strip out the three 'S' symbols, de-interleave, and decode the remaining 66 symbols and
place the resulting 12 bytes into the Data Block Buffer, setting the BFREE and IRQ bits of the Status Register
to '1' when the task is complete.
If an 'Intermediate' block is received, then the µC should read out all 12 bytes from the Data Block Buffer and
ignore the CRCERR bit of the Status Register. For a 'Last' block the µC need only read the first 8 bytes from
the Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2
checksum.
As each of the three 'S' symbols of the block is received, the SVAL bits of the Status Register will be updated
and the SRDY bit set to '1'. (If the SSIEN bit of the Mode Register is '1', then the Status Register IRQ bit will
also be set to '1'.) Note that when the third 'S' symbol is received, the SRDY bit will be set to '1' coincidentally
with the BFREE bit also being set to '1'.
4.5.2.11 SFS: Search for Frame Sync
This task, which is intended for special test and channel monitoring purposes, performs the first two parts only
of a SFP task. It causes the modem to search the received signal for a 24-symbol sequence, which matches
the required Frame Synchronization pattern to within the tolerance defined by the FSTOL bits of the Mode
Register.
When a match is found the modem will read in the following 'S' symbol, then set the BFREE, IRQ, and SRDY
bits of the Status Register to '1' and update the SVAL bits. The µC may then write the next task to the
Command Register.
4.5.2.12 R4S: Read 4 Symbols
This task causes the modem to read the next 4 symbols and translate them directly (without de-interleaving or
FEC) to an 8-bit byte which is placed into the Data Block Buffer. The BFREE and IRQ bits of the Status
Register are then set to '1' to indicate that the µC may read the data byte from the Data Block Buffer and write
the next task to the Command Register.
This task is intended for special tests and channel monitoring - perhaps preceded by a SFS task.
Note: It is possible to construct message formats, which do not rely on the block formatting of the THB, TIB,
and TLB tasks. This can be accomplished by using T4S or T24S tasks to transmit and R4S to receive the
user's data. One should be aware, that the receive level and timing measurement circuits need to see a
reasonably 'random' distribution of all four possible symbols in the received signal to operate correctly.
Accordingly, binary data may benefit from scrambling before transmission if it is not reasonably 'random' to
start with.
4.5.2.13 RSID: Read Station ID
This task causes the modem to read in and decode the following 23 symbols as Station ID data followed by an
'S' symbol. It is similar to the last two parts of a SFP task except that it will not restart if the received CRC0 is
incorrect. It would normally follow a SFS task.
The three decoded bytes will be placed into the Data Block Buffer, and the CRCERR bit of the Status Register
set to '1' if the received CRC0 is incorrect, otherwise it will be cleared to '0'. The SVAL bits of the Status
Register will be updated and the BFREE, SRDY, and IRQ bits set to '1' to indicate that the PC may read the
three received bytes from the Data Block buffer and write the next task to the modem's Command Register.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480171.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CMLMICRO [ CML MICROCIRCUITS ]
