4-Level FSK Modem Data Pump
Page 26 of 50
MX929B PRELIMINARY INFORMATION
otherwise pull the PLL away from its optimum timing. In this case however; it is recommended that the
PLLBW bits only be set to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth'
mode for about 200 symbol times to ensure accurate lock has first been achieved.
The 'Hold' setting disables the feedback loop of the PLL which continues to run at a rate determined only by
the actual crystal frequency and the setting of the Control Register CKDIV bits, not the PLL's operating
frequency immediately prior to the 'Hold' setting.
4.5.4 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register
7 6 5 4 3 2 1 0
IRQEN
INVSYM
RXEYE PSAVE SSIEN
SSYM
Tx/Rx
4.5.4.1 Mode Register B7: IRQEN - IRQ Output Enable
When this bit is set to '1', the IRQ chip output pin is pulled low (V ) given the IRQ bit of the Status Register
SS
is a '1'.
4.5.4.2 Mode Register B6: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
B6
0
Symbol
Signal at TXOUT
Signal at RXAMPOUT
'+3'
Above V
Below V
BIAS
BIAS
'-3'
Below V
Above V
BIAS
BIAS
1
'+3'
'-3'
Below V
Above V
Above V
Below V
BIAS
BIAS
BIAS
BIAS
Note: B6 must be normally set to the same value in Tx and Rx devices for successful communication between
them.
4.5.4.3 Mode Register B5: TX/RX - Tx/Rx Mode
Setting this bit to '1' places the modem into the Transmit mode, clearing it to '0' puts the modem into the
Receive mode.
Note: Changing between receive and transmit modes will cancel any current task.
©2001 MX-COM, INC.
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Doc. # 20480171.003
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