Application Information ......
Rx FREQUENCY
DISCRIMINATOR
SIGNAL AND
DC LEVEL
ADJUSTMENT
FREQUENCY
MODULATOR
Rx SIGNAL IN
Rx FEEDBACK
SIGNAL AND
DC LEVEL
ADJUSTMENT
Tx
CIRCUITS
Tx OUT
Rx
CIRCUITS
µCONTROLLER
RxC
TxD
or UART
TxC
RxD
Rx
Rx
Tx
Tx
DATA
CLOCK
DATA
CLOCK
FX589
GMSK MODEM
Fig.3 External Signal Paths
Clock Oscillator and Dividers
The Tx and (nominal) Rx data rates are determined
by division of the frequency present at the Xtal pin,
which may be generated by the on-chip Xtal oscillator
or be derived from an external source. Any Xtal/clock
frequency in the range 1.0MHz to 5.0MHz (V
DD
= 3.0V)
or 1.0MHz to 8.2MHz (V
DD
= 5.0V) may be employed,
depending upon the desired data rate.
Note
the device operation is not guaranteed
above 64,000 bits/s or below 4,000 bits/s at
the relevant supply voltage
A division ratio to facilitate data-rate setting is
controlled by the logic level inputs on the ClkDivA/B
pins, and is shown in Table 1 (below) - together with
examples of how various ‘standard’ data-rates may be
derived from common µP or Xtal frequencies.
Data Rate =
Xtal/Clock Frequency
Division Ratio (ClkDivA/B)
Xtal/Clock Frequency (MHz)
4.9152
4.096
2.4576
[12.288/3]
[12.288/5]
Data Rate (b/s)
2.048
[6.144/3]
8.192
Inputs
Division Ratio:
ClkDiv ClkDiv
Xtal Freq
A
B
Data Rate
0
0
128
0
1
256
1
0
512
1
1
1024
Table 1 Clock/Data Rates
64000*
32000
16000
8000
38400*
19200
9600
4800
32000
16000
8000
4000
19200
9600
4800
16000
8000
4000
* V
DD
>= 4.5V
Fig.4 Minimum µController System Connections
5
CMLMICRO [ CML MICROCIRCUITS ]
