Application Information
V
DD
XTAL
C
3
X
1
R
2
1
C
4
XTAL
XTAL/CLOCK
ClkDivA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
V
DD
Rx S/N
Tx CLOCK
Rx CLOCK
Rx DATA
Tx DATA
Tx PS
Tx ENABLE
Tx OUT
BT
Doc2
Doc1
R
1
V
SS
C
2
V
SS
XTAL/CLOCK
2
ClkDivB
Rx HOLD
RxDCacq
PLLacq
Rx PS
V
BIAS
FX589P
19
18
17
16
15
14
13
R
4
R
3
C
6
Rx FEEDBACK
Rx SIGNAL IN
V
SS
C
5
C
7
V
SS
C
8
C
1
External Components
Component
R
1
R
2
R
3
R
4
C
1
C
2
Value
Note 1
1.0MΩ
Note 2
100kΩ
Note 1
Note 5
Tolerance
±5%
±10%
±10%
±10%
±10%
C
3
C
4
C
5
C
6
C
7
C
8
X
1
Note 5
100nF
1.0µF
22.0pF
Note 4
Note 4
Note 3
±20%
±20%
±20%
Fig.2 Recommended External Components
Notes
1. The RC network formed by R
1
and C
1
is required
between the Tx Out pin and the input to the
modulator. This network, which can form part of any
dc level shifting and gain adjustment circuitry, forms
an important part of the transmit signal filtering.
The ground connection to the capacitor C
1
should be
positioned to give maximum attenuation of high-
frequency noise into the modulator.
The component values should be chosen so that the
product of the resistance (Ohms) and the capacitance
(Farads) is: BT of 0.3 = 0.34/bit rate (bits/second)
BT of 0.5 = 0.22/bit rate (bits/second).
Data Rate
(b/s)
4000
4800
8000
9600
16000
19200
32000
38400*
64000*
* V
DD
>= 4.5V
BT = 0.3
R1 (kΩ) C1 (pF)
120
680
100
680
91
470
91
390
47
470
100
180
47
220
47
180
56
100
BT = 0.5
R1 (kΩ) C1 (pF)
120
470
100
470
120
220
47
470
91
150
91
120
47
150
47
120
51
68
2. R
3
, R
4
and C
6
form the gain components for the Rx
Input signal. R
3
should be chosen as required by the
signal input level.
3. The FX589 can operate correctly with Xtal/Clock
frequencies of 1.0MHz to 8.2MHz (V
DD
= 5.0V) and
1.0MHz to 5.0MHz (V
DD
= 3.0V); see Table 1 for
examples. Operation of this device without a Xtal or
Clock input may cause device damage.
4. C
7
and C
8
should both be 15.0nF for a data rate of
8kb/s, and inversely proportional to the data rate for
other data rates, e.g. 30.0nF at 4kb/s, 1.8nF at
64kb/s.
5. The value chosen for C
2
and C
3
(including stray
capacitances) should be suitable for the applied V
DD
and the frequency of X
1
.
As a guide: C
2
= C
3
= 33.0pF at 1.0MHz falling to
18pF at the maximum frequency.
At 3 volts, C
2
= C
3
= 33.0pF falling to 18pF at 5.0MHz.
The equivalent series resistance of X
1
should be less
than 2.0kΩ falling to 150Ω at the maximum frequency.
Stray capacitance on the Xtal/clock circuit pins must
be minimised.
Note that in all cases, the value of R
1
should be not less
than 47.0kΩ and that the calculated value of C
1
includes
calculated parasitic (circuit) capacitances.
4
CMLMICRO [ CML MICROCIRCUITS ]
