Application Information ......
PLLacq Rx Hold
PLL Action
“1”
X
Acquire: Sets the PLL bandwidth wide enough to allow a lock to the received signal in
less than 8 zero crossings. This mode will operate as long as PLLacq is a logic “1”.
Medium Bandwidth: The correction applied to the extracted clock is limited to a
maximum of ±1/16th bit-period for every two received zero-crossings. The PLL operates
in this mode for a period of about 30 bits immediately following a “1” to “0” transition of the
PLLacq input, provided that the Rx Hold input is a logic “1”.
“1” to “0”
“1”
Narrow Bandwidth: The correction applied to the extracted clock is limited to a maximum
of ±1/64th bit-period for every two received zero-crossings. The PLL operates in this
mode whenever the Rx Hold Input is a logic “1” and PLLacq has been a logic “0” for at
least 30 bit periods (after Medium Bandwidth operation for instance).
“0”
“0”
“1”
“0”
Hold: The PLL feedback loop is broken, allowing the Rx Clock to freewheel during signal
fade periods.
Rx Level Measure Action
RxDCacq Rx Hold
Clamp: Operates for one bit-time after a “0” to “1” transition of the RxDCacq input. The
external capacitors are rapidly charged towards a voltage mid-way between the received
signal input level and VBIAS, with the charge time-constant being of the order of 0.5bit-time.
“0” to “1”
X
Fast Peak Detect: The voltage detectors act as peak-detectors, one capacitor is used to
capture the ‘positive’-going signal peaks of the Rx Filter output signal and the other capturing
the ‘negative’-going peaks. The detectors operate in this mode whenever the RxDCacq input
is at a logic “1,” except for the initial 1-bit Clamp-mode time.
“1”
X
Averaging Peak Detect: Provides a slower but more accurate measurement of the signal
peak amplitudes.
“0”
“0”
“1”
“0”
Hold: The capacitor charging circuits are disabled so that the outputs of the voltage detectors
remain substantially at the last readings (discharging very slowly [time-constant approx.
2,000bits] towards VBIAS).
Table 2 PLL and Rx Level Measurement Operational Modes
X = don't care
Rx Data Extraction
Rx Clock Extraction
The ‘Rx Data Extraction’ circuit decides whether
each received bit is a “1” or “0” by sampling the output
of the Rx Filter in the middle of each bit-period, and
comparing the sampled voltage against a threshold
derived from the ‘Level Measuring’ circuit. This
threshold is varied on a bit-by-bit basis to compensate
for intersymbol interference depending on the chosen
BT. The extracted data is output from the ‘Rx Data’
pin, and should be sampled externally on the rising
edge of the ‘Rx Clock.’
Synchronized by a phased locked loop (PLL)
circuit to zero-crossings of the incoming data, the ‘Rx
Clock Extraction’ circuitry controls the ‘Rx Clock’
output. The Rx Clock is also used internally by the
Data Extraction circuitry. The PLL parameters can be
varied by the ‘Rx Circuit Control’ inputs PLLacq and Rx
Hold to operate in one of four PLL modes as described
in Table 2.
Rx S/N Detection
The ‘Rx S/N Detector’ system classifies the
incoming zero-crossings as GOOD or BAD depending
upon the time when each crossing actually occurs with
respect to its expected time as determined by the
Clock Extraction PLL. This information is then
processed to provide a logic level output at the ‘Rx
S/N’ pin; a ‘high’ level indicates a series of GOOD
crossings, a ‘low‘ level indicates a BAD crossing.
By averaging this output it is possible to derive a
measure of the Signal-to-Noise-Ratio and hence the
Bit-Error-Rate of the received signal.
7
CMLMICRO [ CML MICROCIRCUITS ]
