AIS Baseband Processor
CMX910
5.3
Reset and Power Control
5.3.1 RESETN pin
The CMX910 is reset by taking RESETN low, which causes all internal clocks and bias currents to be
disabled and all C-BUS registers to be reset. To bring the CMX910 out of this quiescent state after
RESETN is pulled high, a stable clock signal must first be applied to the REFCLK input pin (any multiple
of 2.4MHz up to a maximum of 24MHz), then the Clock_Control register must be programmed with the
frequency of the applied REFCLK. A period of 10ms must then elapse to allow the CMX910 to initialise,
after which time the device is ready for operation. During operation the main Rx and Tx channel analogue
circuits and auxiliary ADC and DAC circuits will be powered up as required, depending on how the host
µC sets various C-BUS control and configuration registers.
5.3.2 General_Reset Command
General_Reset command (no data)
C-BUS Address $01
This command disables all internal bias currents and resets all C-BUS registers except for CBUS_Expand
and Clock_Control. This means that if the CMX910’s internal clocks are running, they will remain running
when General_Reset is applied. After a General_Reset command, a period of 10ms must elapse to allow
the CMX910 to initialise before any further C-BUS operations are attempted.
5.3.3 Clock Control
The CMX910 can be put back into a low power state at any time by writing $00 to the Clock_Control
register. This will disable all internal clocks and bias currents and reset all internal C-BUS registers except
for CBUS_Expand. To subsequently bring the CMX910 out of this low power state requires the same
sequence of operations as if a RESETN pulse had been applied.
Clock_Control register: 8-bit write only.
C-BUS Address $02
All bits cleared to 0 when RESETN pin asserted. Register contents are not affected by a General_Reset
command. This register can be written while the CMX910’s internal clocks are disabled.
7
6
5
4
3
2
1
0
Bit:
Reserved, set to 0000
REFCLK mult. factor
Clock_Control register b3-0: REFCLK Multiplication Factor
b3
b2
b1
b0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Internal clocks disabled, device held in low power mode
REFCLK = 2.4MHz
REFCLK = 4.8MHz
REFCLK = 7.2MHz
REFCLK = 9.6MHz
REFCLK = 12.0MHz
REFCLK = 14.4MHz
REFCLK = 16.8MHz
REFCLK = 19.2MHz
REFCLK = 21.6MHz
REFCLK = 24.0MHz
Codes 10112 to 11112 are reserved, do not use
© 2009 CML Microsystems Plc
12
D/910/6
CMLMICRO [ CML MICROCIRCUITS ]
