Marine VHF Audio and Signalling Processor
CMX885
7.8.2 WAT Detection
The WAT detector is enabled by setting the NWR bit $C1:b12 and indicated by setting b15 of the
NWRData register ($BB). If enabled, the NWR IRQ bit in the Status register $C6:b14 will also be set. The
detector will be reset after 500ms, so multiple detections may be indicated on long WAT tones.
7.8.3 SAME Decoding
The SAME data is received at 520.83bps and decoded by the CMX885 whenever the NWR bit $C1:b12 is
set. Internally, the CMX885 monitors the selected input until it detects the preamble sequence and then
passes the subsequently recovered data to the host uC via the NWR Data register ($BB). The decoder
will detect the data header and determine if it is “ZCZC” indicating that data follows or “NNNN” indicating
the end of a transmission and report these states in bits 13 and 14 of the NWR Data register ($BB)
respectively). If enabled, the NWR IRQ bit in the Status register $C6:b14 will also be set following the
detection of the preamble and on every subsequently received byte.
When the En_NWR_data bit is set, the receiver outputs the received bitstream. The host is allowed to set
this bit at any time to get "raw mode" data output with no preamble/header detection and no guarantee of
byte alignment.
When the En_NWR_data bit is clear, the receiver searches for a valid SAME transmission but does not
output data. If it sees a preamble followed by the data header ("ZCZC"), it raises an IRQ and
*automatically* sets the En_NWR_data bit to put itself into data-output mode. It is then up to the host to
decide when to clear the En_NWR_data bit to put the receiver back into sync-search mode (thus "re-
arming" it).
If the receiver sees a preamble followed by the end-of-message header ("NNNN") while doing sync-
search, it informs the host [2] and then continues the search without putting itself into data-output mode.
It is the responsibility of the host to shut the decoder down at the end of a received burst by clearing the
En_NWR_data bit $C7:b12 to 0.
7.9
Auxiliary ADC Operation
The input to the Auxiliary ADCs can be independently routed to any of the signal input pins under control
of the AuxADC and Tx MOD mode register, $A7. Conversions will be performed as long as a valid input
source is selected; to stop the ADC, the input source should be set to “none”. Register $C0:b6, BIAS,
must be enabled for Auxiliary ADC operation.
Averaging can be applied to the ADC readings by selecting the relevant bits in the AuxADC and Tx MOD
mode register, $A7, the length of the averaging is determined by the value in the Program Blocks P3.0
and P3.1, and defaults to a value of 0. This is a rolling average system such that a proportion of the
current data will be added to the last value. The proportion is determined by the value of the average
counter in P3.0 and P3.1. For an average value of 0; 50% of the current value will be applied, for a value
of 1 = 25%, 2 = 12.5% etc. The maximum useful value of this field is 8. Averaging will begin with the
current value of the AuxADC, therefore it is recommended that the AuxADC be enabled for at least one
sample (250µs) before starting the average process to ensure that its initial value is as expected,
otherwise the initial value will default to zero.
High and low thresholds may be independently applied to both ADC channels (the comparison is applied
after averaging, if this is enabled) and an IRQ generated when either the high threshold is crossed by a
rising edge signal or the low threshold is passed by a falling edge signal, which allows the user to
implement a selectable degree of hysterisis. The thresholds are programmed via the AuxADC Threshold
register, $B5.
Auxiliary ADC data is read back in the AuxADC Data register ($A9) and includes the threshold status as
well as the actual conversion data (subject to averaging, if enabled).
See:
o
o
o
o
AuxADC and Tx MOD Mode – $A7 write
AuxADC1 Data – $A9 read
AuxADC2 Data – $AA read
AuxADC Threshold Data – $B5 write
© 2010 CML Microsystems Plc
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D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
