Marine VHF Audio and Signalling Processor
CMX885
selecting the appropriate source with $C1:b4. Note that, due to the C-BUS latency times, there should be
a delay after clearing this bit, before re-enabling it again.
With DSC mode selected $C7:b8 to b3 and $C7:b1 to b0 are ignored.
Two modes of operation are provided:
o
o
Raw Mode
Formatted Mode
No.
and bit position
12345678910
No.
and bit position
12345678910
No.
and bit position
12345678910
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
BBBBBBBYYY
YBBBBBBYYB
BYBBBBBYYB
YYBBBBBYBY
BBYBBBBYYB
YBYBBBBYBY
BYYBBBBYBY
YYYBBBBYBB
BBBYBBBYYB
YBBYBBBYBY
BYBYBBBYBY
YYBYBBBYBB
BBYYBBBYBY
YBYYBBBYBB
BYYYBBBYBB
YYYYBBBBYY
BBBBYBBYYB
YBBBYBBYBY
BYBBYBBYBY
YYBBYBBYBB
BBYBYBBYBY
YBYBYBBYBB
BYYBYBBYBB
YYYBYBBBYY
BBBYYBBYBY
YBBYYBBYBB
BYBYYBBYBB
YYBYYBBBYY
BBYYYBBYBB
YBYYYBBBYY
BYYYYBBBYY
YYYYYBBBYB
BBBBBYBYYB
YBBBBYBYBY
BYBBBYBYBY
YYBBBYBYBB
BBYBBYBYBY
YBYBBYBYBB
BYYBBYBYBB
YYYBBYBBYY
BBBYBYBYBY
YBBYBYBYBB
BYBYBYBYBB
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
YYBYBYBBYY
BBYYBYBYBB
YBYYBYBBYY
BYYYBYBBYY
YYYYBYBBYB
BBBBYYBYBY
YBBBYYBYBB
BYBBYYBYBB
YYBBYYBBYY
BBYBYYBYBB
YBYBYYBBYY
BYYBYYBBYY
YYYBYYBBYB
BBBYYYBYBB
YBBYYYBBYY
BYBYYYBBYY
YYBYYYBBYB
BBYYYYBBYY
YBYYYYBBYB
BYYYYYBBYB
YYYYYYBBBY
BBBBBBYYYB
YBBBBBYYBY
BYBBBBYYBY
YYBBBBYYBB
BBYBBBYYBY
YBYBBBYYBB
BYYBBBYYBB
YYYBBBYBYY
BBBYBBYYBY
YBBYBBYYBB
BYBYBBYYBB
YYBYBBYBYY
BBYYBBYYBB
YBYYBBYBYY
BYYYBBYBYY
YYYYBBYBYB
BBBBYBYYBY
YBBBYBYYBB
BYBBYBYYBB
YYBBYBYBYY
BBYBYBYYBB
YBYBYBYBYY
86
87
88
89
90
91
92
93
94
95
96
97
98
BYYBYBYBYY
YYYBYBYBYB
BBBYYBYYBB
YBBYYBYBYY
BYBYYBYBYY
YYBYYBYBYB
BBYYYBYBYY
YBYYYBYBYB
BYYYYBYBYB
YYYYYBYBBY
BBBBBYYYBY
YBBBBYYYBB
BYBBBYYYBB
YYBBBYYBYY
BBYBBYYYBB
YBYBBYYBYY
BYYBBYYBYY
YYYBBYYBYB
BBBYBYYYBB
YBBYBYYBYY
BYBYBYYBYY
YYBYBYYBYB
BBYYBYYBYY
YBYYBYYBYB
BYYYBYYBYB
YYYYBYYBBY
BBBBYYYYBB
YBBBYYYBYY
BYBBYYYBYY
YYBBYYYBYB
BBYBYYYBYY
YBYBYYYBYB
BYYBYYYBYB
YYYBYYYBBY
BBBYYYYBYY
YBBYYYYBYB
BYBYYYYBYB
YYBYYYYBBY
BBYYYYYBYB
YBYYYYYBBY
BYYYYYYBBY
YYYYYYYBBB
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
B = 0
Y = 1
Order of transmitted bits: bit 1 first
Figure 12 DSC character format
7.7.1 Receiving DSC Signals
The received signal is filtered and data is extracted with the aid of a PLL to recover the clock from the
serial data stream. The recovered data is stored in a 2-byte buffer (grouped into 16-bit words) and an
interrupt issued to indicate received data is ready. Data is transferred over the C-BUS under host µC
control. If this data is not read before the next data is decoded it will be overwritten and it is up to the user
to ensure that the data is transferred at an adequate rate following data ready being flagged. The DSC bit
clock is not output externally.
© 2010 CML Microsystems Plc
25
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
