Marine VHF Audio and Signalling Processor
CMX885
7.11 Digital System Clock Generator
to RF Synthesiser
Ref CLK selection
SYSCLK1 VCO
24.576-
98.304MHz
LPF
VCO
VCO
VCO
(49.152MHz typ)
Ref CLK div
/1 to 512
PLL div
/1 to 1024
$AB b0-9
PD
SYSCLK1
Ref
SYSCLK1
Div
$AC b0-8
48 - 192kHz
(96kHz typ)
VCO op div
/1 to 64
$AB b10-15
SYSCLK1
Pre-CLK
$AC b11-15
SYSCLK1
Output
384kHz-20MHz
SYSCLK2 VCO
24.576-
98.304MHz
LPF
(49.152MHz typ)
Ref CLK div
/1 to 512
PLL div
/1 to 1024
$AD b0-9
PD
SYSCLK2
Ref
SYSCLK2
Div
$AE b0-8
48 - 192kHz
(96kHz typ)
VCO op div
/1 to 64
$AD b10-15
SYSCLK2
Pre-CLK
$AE b11-15
SYSCLK2
Output
384kHz-20MHz
MainCLK VCO
24.576-
LPF
98.304MHz
(49.152MHz typ)
Ref CLK div
/1 to 512
P3.4
PLL div
/1 to 1024
P3.5
PD
MainCLK
Ref
MainCLK
Div
48 - 192kHz
(96kHz typ)
VCO op div
/1 to 64
P3.3 b12-7
P3.6 b12-7
MainCLK
Output
384kHz-50MHz
(24.576MHz typ)
MainCLK
Pre-CLK
To Internal
ADC / DAC
dividers
3.0 - 12.288MHz Xtal
AuxADC
Div
P3.3 b6-0
P3.6 b6-0
OSC
or
3.0 - 24.576MHZ Clock
Aux_ADC
(83.3kHz typ)
Figure 13 Digital Clock Generation Schemes
The CMX885 includes a 2-pin crystal oscillator circuit. This can either be configured as an oscillator, as
shown in section 5, or the XTAL input can be driven by an externally generated clock. The crystal (Xtal)
source frequency can go up to 12.288MHz (clock source frequency up to 24.576MHz), but by default, a
3.6864MHz Xtal is assumed for the functionality provided in the CMX885.
7.11.1 Main Clock Operation
A PLL is used to create the main clock (MainCLK - nominally 24.576MHz) for the internal sections of the
CMX885. At the same time, other internal clocks are generated by division of either the Xtal Reference
Clock or the Main Clock. These internal clocks are used for determining the sample rates and conversion
times of A-to-D and D-to-A converters, running a General Purpose Timer, the signal processing block. In
particular, it should be noted that in Idle mode the setting of the GP Timer divider directly affects the C-
BUS latency (with the default values this is nominally 250μs).
© 2010 CML Microsystems Plc
31
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
