Marine VHF Audio and Signalling Processor
CMX885
The extracted data is compared with the 16-bit programmed Frame Sync pattern (preset to $CB23
following a RESET command). An interrupt will be flagged when the programmed Frame Sync pattern is
detected. The host µC may stop the frame sync search by disabling the DSC demodulator ($C1:b2
cleared to 0). Once a valid Frame Sync pattern has been detected, the frame sync search algorithm is
disabled; it may be re-started by the host disabling the Modem Enable bit of the Mode Control register
($C1:b2) and then re-enabling it (taking note of the C-BUS latency time).
In Rx Raw mode (En_RAW=1) the modem will report back all data received as soon as it is enabled.
(Note: If a valid DSC signal is not present when the modem is first enabled, it will still attempt to
demodulate the input signal and output data. The host must determine if the data is valid or not. It is
possible to use the SynC facility to reduce the amount of invalid data presented to the host, but this may
also lead to DSC calls with errors in the SynC pattern being missed).
As soon as the Modem Enable bit has been asserted, the modem will attempt to demodulate the input
signal. Data bits will then be delivered to the Rx Data 1 register, $C5 as they are demodulated, indicated
by the Data_RDY bit. It is up to the host to align, decode and validate the data and to subsequently switch
the modem off once an EOS (End of Sequence) has been detected (by clearing $C1:b2 to 0). In this
mode, the device does not perform byte alignment or phasing (synchronisation) detection2.
The host must read the RxData 1 register before the next 16 bits of data have been received, otherwise
the data will be lost.
If the SynC facility is used in Raw mode, then the value of SynC must be programmed by the host to a
suitable value via the Program Blocks, P0.0 and P0.1. The values $5555 or $AAAA are suggested for this
setting, however, this will not completely remove false detections and the following received data must be
analysed before assuming that a valid call is in progress (see ITU-R M.493-11 for details). The SynC
enable bit $C7:b15 must be asserted. Setting the Modem Enable bit $C1:b2 will activate the DSC modem,
which will then attempt to decode the signal at its input. Acquisition of the SynC data pattern will be
reported to the host by the setting of the DSC bit $C6:b3.
In Rx Formatted mode, (En_Raw=0) the modem will check the incoming bit stream for a valid sequence
of phasing characters (3x Rx, 2x Dx+ Rx or Dx + 2 x Rx) and then report any correctly decoded
characters in the RxData1 ($C5) register. The characters are packed into the 16-bit register as two 7-bit
characters and an additional error indication bit (bits 15 and 7). In the case where an odd number of
characters has been received, the unused field will be reported as 0000000. This mechanism significantly
reduces the amount of data transferred to the host and the host processing requirements.
The decoded 7-bit characters will be delivered to the RxData1 register, $C5, as indicated by the
Data_RDY bit. The modem will not report valid data until it has correctly received the initial phasing
sequence. Once the Phasing sequence has been detected, the modem’s internal DPLL bandwidth will be
automatically reduced to improve the error performance. If one of the time-diversity received characters is
in error, only the correct one will be reported. If both characters have errors, the last one received will be
reported, with bit 7 (MSB) set. The characters reported back will correspond to the data sequence (see
Figure 11)3:
A A B1 B2 B3 B4 B5 C D1 D2 D3 D4 D5 E1 E2 F1 F2 F3 G1 G2 G3 H I
Once the H and I fields have been received by the host, it should shut the DSC modem down by clearing
the Modem Enable bit in the Mode Control register $C1:b2.
7.7.2 Transmitting DSC Signals
The DSC encoding operates in accordance with the bit settings in the Modem Configuration register
($C7). When enabled the modulator will begin transmitting data using the settings and values in Program
Block 0 (bit sync and frame sync patterns), the Modem Configuration register and the Tx Data registers.
Therefore, these registers should be programmed to the required values before transmission is enabled.
2 This is similar to the FX604, CMX910 and CMX7032 operation.
3 This particular sequence corresponds to the example given in ITU-R M493-11. Different Telecommands
will produce different sequences of varying lengths.
© 2010 CML Microsystems Plc
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D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
