Marine VHF Audio and Signalling Processor
CMX885
The CMX885 defaults to the settings appropriate for a 3.6864MHz Xtal, however if other frequencies are
to be used (to facilitate commonality of Xtals between external RF synthesizers and the CMX885 for
instance) then the Program Block registers P3.2 to P3.7 will need to be programmed appropriately at
power-on. A table of common values is provided in Table 2.
See:
o
Program Block 3 – AuxDAC, RAMDAC and Clock Control
7.11.2 System Clock Operation
Two System Clock outputs, SYSCLK1 and SYSCLK2, are available to drive additional circuits, as
required. These are phase locked loop (PLL) clocks that can be programmed via the System Clock
registers with suitable values chosen by the user. The System Clock PLL Configure registers ($AB and
$AD) control the values of the VCO Output divider and Main Divide registers, while the System Clock Ref.
Configure registers ($AC and $AE) control the values of the Reference Divider and signal routing
configurations. The PLLs are designed for a reference frequency of 96kHz. If not required, these clocks
can be independently powersaved. The clock generation scheme is shown in the block diagram of Figure
13. Note that at power-on, these outputs are disabled.
See:
o
o
SYSCLK1 and SYSCLK2 PLL Data – $AB, $AD write
SYSCLK1 and SYSCLK2 REF – $AC and $AE write
7.12 GPIO
Two pins are provided for control of external hardware. RXENA and TXENA are driven by the device to
follow the state of the Rx and Tx Mode bits in the Mode register, $C1:
$C1 Mode:
Idle
Rx
Tx
reserved
b1
0
0
1
1
b0
0
1
0
1
TXENA
RXENA
1
1
0
1
1
0
1
1
7.13 Signal Level Optimisation
The internal signal processing of the CMX885 will operate with wide dynamic range and low distortion
only if the signal level at all stages in the signal processing chain is kept within the recommended limits.
For a device working from a 3.3V ±10% supply, the maximum signal level which can be accommodated
without distortion is [(3.3 x 90%) – (2 x 0.3V)] Volts pk-pk = 838mVrms, assuming a sine wave signal.
Compared to the reference level of 308mVrms, this is a signal of +8.69dB. This level should not be
exceeded at any stage.
7.13.1 Transmit Path Levels
For the maximum signal out of the MOD1 and MOD2 attenuators, the signal level at the output of the
Analogue Routing block should not exceed +8.69dB, assuming both fine and coarse output attenuators
are set to a gain of 0dB. This means that the output from the soft limiter must not exceed 838mVrms. If
pre-emphasis is used, an output signal at 3000Hz will have three times the amplitude of a signal at
1000Hz, so the signal level before pre-emphasis should not exceed 279mVrms. The Fine Input Gain
adjustment has a maximum attenuation of 3.5dB and no gain, whereas the Coarse Input Gain adjustment
has a variable gain of up to +22.4dB and no attenuation. If the highest gain setting were used, then the
maximum allowable input signal level at the MICFB pin would be 54mVrms. With the lowest gain setting
(0dB), the maximum allowable input signal level at the MICFB pin would be 718mVrms.
7.13.2 Receive Path Levels
For the maximum signal out of the AUDIO attenuator, the signal level at the output of the Analogue
Routing block should not exceed +8.69dB, assuming both fine and coarse output attenuators are set to a
gain of 0dB. That is a signal level of 838mVrms. If de-emphasis is used, an output signal at 300Hz will
have three and one third times the amplitude of a signal at 1000Hz, so the signal level before de-
© 2010 CML Microsystems Plc
32
D/885/3
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