Marine VHF Audio and Signalling Processor
CMX885
emphasis should not exceed 251mVrms. The Fine Input Gain adjustment has a maximum attenuation of
3.5dB and no gain, whereas the Coarse Input Gain adjustment has a variable gain of up to +22.4dB and
no attenuation. If the highest gain setting were used, then the maximum allowable input signal level at the
DISCFB pin would be 12.0mVrms. With the lowest gain setting (0dB), the maximum allowable input
signal level at the DISCFB pin would be 158mVrms. The signal level of +8.69dB (838mVrms) is an
absolute maximum, which should not be exceeded anywhere in the signal processing chain if severe
distortion is to be avoided.
AUDIO
OUT
Tone Level: $CD:001x
Input1 Gain: $B1:b12-10
or P1.0
In-band Tones,
Audio Tones
and DSC/ATIS
Modem
Output1
Input1
Fine gain: P4.0
DISC
ALT
Coarse Gain: $B0:b3-0
Tx Mult x2,x4,x8:
$CD:101x
Fine Gain: $CD:110x
MUX
MOD1
Fine gain:
P4.2 or $CD:011x
Offset: P4.4
Voice Processing
MUX
MUX
$A7:
b15-12
MUX
Fine gain:
P4.3 or $CD:100x
Offset: P4.5
$C1:
b15-2
$B1:
b9-6
$B1:
b5-2
$C1:
b15-2
Coarse Gain: $B0:b14-12
Rx Voice Level:
$CD:010x
Fine Gain: $CD:110x
MIC
MOD2
Fine gain: P4.1
Output2
Input2
Input2 Gain: $B1:b15-13
Note:
Rx Voice Level adjust ($CD:010x) is only active in Rx mode
Tx Mult ($CD:101x) is only active in Tx mode
Coarse Gain: $B0:b10-8
Figure 14 Level Adjustments
7.14 C-BUS Interface
7.14.1 Interrupt Operation
The CMX885 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status register and
the IRQ Mask bit (bit 15) are both set to 1. The IRQ bit is set when the state of the interrupt flag bits in the
Status register change from a 0 to 1 and the corresponding mask bit(s) in the Interrupt Mask register
is(are) set. Enabling an interrupt by setting a mask bit (0→1) after the corresponding Status register bit
has already been set to 1 will also cause the IRQ bit to be set.
All interrupt flag bits in the Status register, except the PRG flag (bit 0), are cleared and the interrupt
request is cleared following the command/address phase of a C-BUS read of the Status register. The
PRG flag bit is set to 1 only when it is permissible to write a new word to the Programming register.
See:
o
o
Status – $C6 read
Interrupt Mask – $CE
7.14.2 General Notes
In normal operation, the most significant registers are:
o
o
o
o
o
Mode Control – $C1 write
Status – $C6 read
Analogue Output Gain – $B0 write
Input Gain and Output Signal Routing – $B1 write
Audio Control – $C2 write
Setting the Mode Control register to either Rx or Tx will automatically increase the internal clock speed to
its operational rate, whilst setting the Mode Control register to Idle will automatically return the internal
clock to a lower (powersaving) rate. To access the Program Blocks (through the Programming register,
$C8) the device MUST be in Idle mode.
Under normal circumstances, the CMX885 manages the main clock control automatically, using the
default values loaded in Program Block 3.
© 2010 CML Microsystems Plc
33
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
