TDMA Digital Radio Processor
CMX7161
7.5
Device Control
Device control is primarily carried out by writing and reading registers over the C-BUS interface.
7.5.1 Device Control Overview
The CMX7161 can be set into four main operating modes using the Modem Control Register ($6B write):
Sleep mode – for power saving and device configuration
Transmit mode – for continuous transmission
Receive mode – for detection and reception of continuous data
Slotted mode – for transmission and reception in 30ms slots
To conserve power the device can be placed into Sleep mode when not actively processing a signal.
Additional power-saving can be achieved by disabling unused hardware blocks; however most hardware
power-saving is automatic by default.
A number of other registers are used to configure the device during operation. While in Sleep mode the
Programming Register ($6A write) can also be used to configure device parameters that are changed less
frequently.
Payload data is transferred to and from the host via the Transmit and Receive FIFO buffers.
A dedicated interrupt line is provided to alert the host µC to significant events. Interrupt of different types
can be individually enabled using the IRQ Mask Register ($6C read) and the cause of each interrupt is
reported in the IRQ Status Register ($7E read).
7.5.2 Device Configuration (Programming Register)
The Programming Register ($6A write) gives access to internal device registers which configure device
parameters that are changed less frequently. These will normally need to be modified only at power-on or
during major mode changes (if at all). They can only be accessed while the device is in Sleep mode.
Full details of how to configure these aspects of device operation are given in the User Manual.
7.5.3 Data Transfer
Payload data is transferred to and from the host via the Transmit and Receive FIFO buffers, which provide
efficient streaming C-BUS access to transfer blocks of data with minimal overhead. The FIFOs can be
accessed at any time allowing data to be loaded and retrieved when most convenient.
Each FIFO holds a maximum of 128 bytes of data. Current fill-levels can be determined by reading the
Transmit and Receive FIFO Level Registers ($4B, $4F read). The FIFO Control Register ($50 write) can
be used to set fill-level thresholds which will generate host interrupts on being reached.
7.5.4 Interrupt Operation
The CMX7161 can produce an interrupt output when various events occur such as detection of a frame
synchronisation word or a FIFO threshold being reached.
Each event has an associated IRQ Status register bit and an IRQ Mask register bit. The IRQ Mask register
is used to select which status events will trigger an interrupt on the IRQN line. All events can be masked
using the IRQ mask bit (bit 15) or individually masked using the IRQ Mask register. Enabling an interrupt
by setting a mask bit (01) after the corresponding IRQ Status register bit has already been set to 1 will
also cause an interrupt on the IRQN line. The IRQ bit (bit 15) of the IRQ Status register reflects the IRQN
line state.
All interrupt flag bits in the IRQ Status register are cleared and the interrupt request is cleared following the
command/address phase of a C-BUS read of the IRQ Status register. See:
IRQ Status - $7E, read
IRQ Mask - $6C, write
2013 CML Microsystems Plc
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D/7161_FI-1.0/4
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