CS8900A
Crystal LAN™ Ethernet Controller
bit times), and k is the smaller of n or 10, where
n is the number of retransmission attempts.
transmission. The SQE Test is a 10 MHz sig-
nal lasting 5 to 15 bit times and starting within
0.6 to 1.6 µs after the end of transmission.
During this period, the CS8900A ignores re-
ceive carrier activity (see SQE Error in this
section for more information).
3.9.5.9 Modified Backoff
The Modified Backoff is described by the
equation:
0 ≤ r ≤ 2k
3.10 Encoder/Decoder (ENDEC)
where r (a random integer) is the number of
slot times the MAC must wait, and k is 3 for n
< 3 and k is the smaller of n or 10 for n ≥ 3,
where n is the number of retransmission at-
tempts.
The CS8900A’s integrated encoder/decoder
(ENDEC) circuit is compliant with the relevant
portions of section 7 of the Ethernet standard
(ISO/IEC 8802-3, 1993). Its primary functions
include: Manchester encoding of transmit da-
ta; informing the MAC when valid receive data
is present (Carrier Detection); and, recovering
the clock and NRZ data from incoming
Manchester-encoded data.
The advantage of the Modified Backoff algo-
rithm over the Standard Backoff algorithm is
that it reduces the possibility of multiple colli-
sions on the first three retries. The disadvan-
tage is that it extends the maximum time
needed to gain access to the network for the
first three retries.
Figure 12 provides a block diagram of the EN-
DEC and how it interfaces to the MAC, AUI
and 10BASE-T transceiver.
The host may choose to disable the Backoff al-
gorithm altogether by setting the DisableBack-
off bit (Register 19, TestCTL, Bit B). When
disabled, the CS8900A only waits the 9.6 µs
IPG time before starting transmission.
3.10.1 Encoder
The encoder converts NRZ data from the MAC
and a 20 MHz Transmit Clock signal into a se-
rial stream of Manchester data. The Transmit
Clock is produced by an on-chip oscillator cir-
cuit that is driven by either an external 20 MHz
quartz crystal or a TTL-level CMOS clock in-
put. If a CMOS input is used, the clock should
be 20 MHz 0.01% with a duty cycle between
3.9.5.10 SQE Test
If the CS8900A is transmitting on the AUI, the
external transceiver should generate an SQE
Test signal on the CI+/CI- pair following each
ENDEC
RXSQ L
Carrier
Carrier Sense
Detector
10BASE-T
Transceiver
RX
TX
RX CLK
Decoder
R X
M UX
& P LL
RX N RZ
MAC
AUISQ L
AUIRX
TXCLK
TX N RZ
Encoder
TX
TEN
Port Select
M UX
AUITX
AUI
AUIC ol
Collision
Clock
Figure 12. ENDEC
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