CS8900A
Crystal LAN™ Ethernet Controller
network collisions. The collision count is
stored in bits B through E of the TxEvent reg-
ister (Register 8). If the packet collides 16
times, transmission of that packet is terminat-
ed and the 16coll bit (Register 8, TxEvent, Bit
F) is set. If the 16colliE bit (Register 7, TxCFG,
Bit F) is set, the host will be interrupted on the
16th collision. A running count of transmit col-
lisions is recorded in the TxCOL register.
RxCTL, Bit E) is set, the first 1518 bytes of the
frame will still be buffered by CS8900A. If the
ExtradataiE bit (Register 3, RxCFG. Bit E) is
set, the host is interrupted.
3.9.4.4 Dribble Bits and Alignment Error
Under normal operating conditions, the MAC
may detect up to 7 additional bits after the last
full byte of a receive packet. These bits, known
as dribble bits, are ignored. If dribble bits are
detected, the Dribblebit bit (Register 4, Rx-
Event, Bit 7) is set. If both the Dribblebits bit
and CRCerror bit (Register 4, RxEvent, Bit C)
are set at the same time, an alignment error
3.9.3.6 Transmit Underrun
If the CS8900A starts transmission of a packet
but runs out of data before reaching the end of
frame, the TxUnderrun bit (Register C, BufE-
vent, Bit 9) is set. The MAC then forces a bad has occurred.
CRC and terminates the transmission. If the
3.9.5 Media Access Management
TxUnderruniE bit (Register B, BufCFG, Bit 9)
is set, the host is interrupted.
The Ethernet network topology is a single
shared medium with several attached stations.
The Ethernet protocol is designed to allow
each station equal access to the network at
any given time. Any node can attempt to gain
access to the network by first completing a de-
ferral process (described below) after the last
network activity, and then transmitting a pack-
et that will be received by all other stations. If
two nodes transmit simultaneously, a collision
occurs and the colliding packets are corrupted.
Two primary tasks of the MAC are to avoid net-
work collisions, and then recover from them
when they occur. In addition, when the
CS8900A is using the AUI, the MAC must sup-
port the SQE Test function described in sec-
tion 7.2.4.6 of the Ethernet standard.
3.9.4 Receive Error Detection and Han-
dling
The following receive errors are reported in the
RxEvent register (Register 4):
3.9.4.1 CRC Error
If a frame is received with a bad CRC, the
CRCerror bit (Register 4, RxEvent, Bit C) is
set. If the CRCerrorA bit (Register 5, RxCTL,
Bit C) is set, the frame will be buffered by
CS8900A. If the CRCerroriE bit (Register 3,
RxCFG. Bit C) is set, the host is interrupted.
3.9.4.2 Runt Frame
If a frame is received that is shorter than 64
bytes, the Runt bit (Register 4, RxEvent, Bit D)
is set. If the RuntA bit (Register 5, RxCTL, Bit
D) is set, the frame will still be buffered by
CS8900A. If the RuntiE bit (Register 3, Rx-
CFG. Bit D) is set, the host is interrupted.
3.9.5.1 Collision Avoidance
The MAC continually monitors network traffic
by checking for the presence of carrier activity
(carrier activity is indicated by the assertion of
the internal Carrier Sense signal generated by
the ENDEC). If carrier activity is detected, the
network is assumed busy and the MAC must
wait until the current packet is finished before
3.9.4.3 Extra Data
If a frame is received that is longer than 1518
bytes, the Extradata bit (Register 4, RxEvent,
Bit E) is set. If the ExtradataA bit (Register 5,
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