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CS8900A-IQZ 参数 Datasheet PDF下载

CS8900A-IQZ图片预览
型号: CS8900A-IQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路PC局域网以太网时钟
文件页数/大小: 138 页 / 2374 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ Ethernet Controller  
collision detection, preamble generation and 3.9.2.1 Transmission  
detection, and CRC generation and test. Pro-  
grammable MAC features include automatic  
retransmission on collision, and padding of  
transmitted frames.  
Once the proper number of bytes have been  
transferred to the CS8900A’s memory (either  
5, 381, 1021 bytes, or full frame), and provid-  
ing that access to the network is permitted, the  
MAC automatically transmits the 7-byte pre-  
amble (1010101b...), followed by the Start-of-  
Frame Delimiter (SFD, 10101011b), and then  
the serialized frame data. It then transmits the  
Frame Check Sequence (FCS). The data after  
the SFD and before the FCS (Destination Ad-  
dress, Source Address, Length, and data field)  
is supplied by the host. FCS generation by the  
CS8900A may be disabled by setting the In-  
hibitCRC bit (Register 9, TxCMD, bit C).  
Figure 8 shows how the MAC engine interfac-  
es to other CS8900A functions. On the host  
side, it interfaces to the CS8900A’s internal  
data/address/control bus. On the network  
side, it interfaces to the internal Manchester  
encoder/decoder (ENDEC). The primary func-  
tions of the MAC are: frame encapsulation and  
decapsulation; error detection and handling;  
and, media access management.  
LED  
Logic  
Figure 9 shows the Ethernet frame format.  
3.9.2.2 Reception  
The MAC receives the incoming packet as a  
serial stream of NRZ data from the Manches-  
ter encoder/decoder. It begins by checking for  
the SFD. Once the SFD is detected, the MAC  
assumes all subsequent bits are frame data. It  
reads the DA and compares it to the criteria  
programmed into the address filter (see  
Section 5.2.10 on page 87 for a description of  
Address Filtering). If the DA passes the ad-  
dress filter, the frame is loaded into the  
CS8900A’s memory. If the BufferCRC bit  
(Register 3, RxCFG, bit B) is set, the received  
FCS is also loaded into memory. Once the en-  
Encoder/  
802.3  
Decoder  
CS8900A  
Internal Bus  
10BASE-T  
& AUI  
MAC  
Engine  
&
PLL  
Figure 8. MAC Interface  
3.9.2 Frame Encapsulation and Decapsu-  
lation  
The CS8900A’s MAC engine automatically as-  
sembles transmit packets and disassembles  
receive packets. It also determines if transmit  
and receive frames are of legal minimum size.  
Packet  
Fram e  
up to  
7
bytes  
1
byte  
6
bytes  
6
bytes  
2
bytes  
4 bytes  
alternating 1s / 0s  
SFD  
D A  
SA  
Length Field  
LLC data  
Pad  
FCS  
preamble  
frame length  
min 64 bytes  
m ax 1518 bytes  
Direction of Transm ission  
SFD = Start of Frame Delim iter  
DA = Destination Address  
SA = Source Address  
LLC = Logical Link Control  
FCS = Frame Check Sequence (also  
called C yclic Redundancy Check, or C RC)  
Figure 9. Ethernet Frame Format  
CIRRUS LOGIC PRODUCT DATASHEET  
30  
DS271F4  
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