CS8900A
Crystal LAN™ Ethernet Controller
3.8 LED Outputs
(Register 15, SelfCTL, Bit D) must be clear.
When controlled by the host, BSTATUS is low
whenever the HCB1 bit (Register 15, SelfCTL,
Bit F) is set. To configure it for host control,
HC1E must be set. Table 11 summarizes this
operation.
The CS8900A provides three output pins that
can be used to control LEDs or external logic.
3.8.1 LANLED
LANLED goes low whenever the CS8900A
transmits or receives a frame, or when it de-
tects a collision. LANLED remains low until
there has been no activity for 6 ms (i.e. each
transmission, reception, or collision produces
a pulse lasting a minimum of 6 ms).
HC1E HCB1
(Bit D) (Bit F)
Pin Function
0
N/A
Pin configured as BSTATUS: Output is
low when a receive frame begins trans-
fer across the ISA bus. Output is high
otherwise
3.8.2 LINKLED or HC0
1
1
0
1
Pin configured as HC1:
Output is high
LINKLED or HC0 can be controlled by either
the CS8900A or the host. When controlled by
the CS8900A, LINKLED is low whenever the
CS8900A receives valid 10BASE-T link puls-
es. To configure this pin for CS8900A control,
the HC0E bit (Register 15, SelfCTL, Bit C)
must be clear. When controlled by the host,
LINKLED is low whenever the HCB0 bit (Reg-
ister 15, SelfCTL, Bit E) is set. To configure it
for host control, the HC0E bit must be set. Ta-
ble 10 summarizes this operation.
Pin configured as HC1:
Output is low
Table 11. BSTATUS/HCI Pin Operation
3.8.4 LED Connection
Each LED output is capable of sinking 10 mA
to drive an LED directly through a series resis-
tor. The output voltage of each pin is less than
0.4 V when the pin is low. Figure 7 shows a
typical LED circuit.
+5V
HC0E HCB0
(Bit C) (Bit E)
Pin Function
0
N/A
Pin configured as LINKLED: Output is
low when valid 10BASE-T link pulses
are detected. Output is high if valid link
pulses are not detected
1
1
0
1
Pin configured as HC0:
Output is high
LAN LED
Pin configured as HC0:
Output is low
LINKLED
Table 10. LINKLED/HC0 Pin Operation
Figure 7. LED Connection Diagram
3.8.3 BSTATUS or HC1
3.9 Media Access Control
BSTATUS or HC1 can be controlled by either
the CS8900A or the host. When controlled by
the CS8900A, BSTATUS is low whenever the
host reads the RxEvent register (PacketPage
base + 0124h), signaling the transfer of a re-
ceive frame across the ISA bus. To configure
this pin for CS8900A control, the HC1E bit
3.9.1 Overview
The CS8900A’s Ethernet Media Access Con-
trol (MAC) engine is fully compliant with the
IEEE 802.3 Ethernet standard (ISO/IEC 8802-
3, 1993). It handles all aspects of Ethernet
frame transmission and reception, including:
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