CS2000-OTP
main unlocked for the specified time listed in the “AC Electrical Characteristics” on page 7 after which lock
will be acquired and the PLL output will resume.
23
23
2
SysClk cycles
2
SysClk cycles
Lock Time
Lock Time
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
23
Figure 7. CLK_IN removed for > 2 SysClk cycles
23
f CLK_IN is removed and then reapplied within 2 SysClk cycles but later than t , the ClkSkipEn pa-
CS
rameter will have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 8).
Once CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the
PLL_OUT state will be determined by the ClkOutUnl parameter during this time.
23
23
2
SysClk cycles
2
SysClk cycles
tCS
tCS
Lock Time
Lock Time
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
23
Figure 8. CLK_IN removed for < 2 SysClk cycles but > t
CS
If CLK_IN is removed and then re-applied within t , the ClkSkipEn parameter determines whether
CS
PLL_OUT continues while the PLL re-acquires lock (see Figure 9). When ClkSkipEn is disabled and
CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go
unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl
parameter during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will
12
DS758PP1
CIRRUS [ CIRRUS LOGIC ]
