CS2000-OTP
5.2.2
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 6. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.
XTI
XTO
40 pF
40 pF
Figure 6. External Component Requirements for Crystal Circuit
5.2.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or terminated through a 47 kΩ resistor to
GND.
5.3
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used in Hybrid PLL Mode by the Digital PLL and Fractional-
N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid An-
alog-Digital PLL” on page 9). The Digital PLL first compares the CLK_IN frequency to the PLL output. The
Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal
timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock
which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference
clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Char-
acteristics” on page 7.
5.3.1
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to 20 ms (t ) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN
CS
skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn global pa-
rameter enables this function.
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Regardless of the setting of the ClkSkipEn parameter the PLL output will continue for 2 SysClk cycles
(466 ms to 1048 ms) after CLK_IN is removed (see Figure 7). This is true as long as CLK_IN does not
glitch or have an effective change in period as the clock source is removed, otherwise the PLL will inter-
23
pret this as a change in frequency causing clock skipping and the 2 SysClk cycle time-out to be by-
passed and the PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and
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2
SysClk cycles pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl
parameter; See “PLL Clock Output” on page 19. If CLK_IN is re-applied after such time, the PLL will re-
DS758PP1
11
CIRRUS [ CIRRUS LOGIC ]
