CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.41 ASTCR (0xCC) — I/O Asynchronous Timing Control
7
6
5
4
3
2
1
0
A X X X X X X X
This register is used where I/O is being used with a very fast memory system clock. Normally it is pro-
grammed to ‘0’to give the minimum delay for these cycles; however, in some configurations it may be nec-
essary to program the register bit to ‘1’ to slow down the internal synchronization between I/O clocks and
memory clocks and thus ensure sufficient address hold time for the I/O address.
A
asynchronous timing control
0
1
minimal delay to I/O cycles
wait states to ensure address hold time
10.3.42 DRAMCR (0xD0) — DRAM Control
7
6
5
4
3
2
1
0
X P R E S S S S
This register selects between 16- and 32-bit modes of operation for each of the four available banks of
DRAM. Each bank can be individually selected for 16 or 32-bit operation. This allows a mixed 16/32-bit-
wide system to be built. It also controls EDO support and some timing options.
P
R
E
RAS precharge time
0
1
3 memory clock cycles guaranteed RAS precharge
4 memory clock cycles guaranteed RAS precharge
RAS-to-CAS delay on read cycles
0
1
2 memory clock cycles from falling nRAS to falling nCAS
3 memory clock cycles from falling nRAS to falling nCAS
EDO memory
0
1
Fast Page memory
EDO memory
S
16- or 32-bit mode select, one for each bank
bit 3, bank 3 DRAM width
Write
0
1
32-bit
16-bit
bit 2, bank 2 DRAM width
0
1
32-bit
16-bit
bit 1, bank 1 DRAM width
0
1
32-bit
16-bit
bit 0, bank 0 DRAM width
0
1
32-bit
16-bit
Read
Reset
reads above values
set bits to ‘0’ (32-bit)
96
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
