CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.38 MSECR (0xAC) — Mouse Control
As KBDCR register.
10.3.39 IOTCR (0xC4) — I/O Timing Control
7
6
5
4
3
2
1
0
X X X X C C S S
This register sets up the cycle types for two areas of I/O space.
C
combo area access speed
NPCCS 1/2 area access speed
bits[7:4] reserved
S
Write
bits[3:2]
00
01
10
11
Type A (slowest)
Type B
Type C
Type D (fastest)
bits[1:0]
00
Type A (slowest)
Type B
01
10
Type C
11
Type D (fastest)
Read
read back the above values
10.3.40 ECTCR (0xC8) — I/O Expansion Card Timing Control
7
6
5
4
3
2
1
0
E E E E E E E E
This register sets up the access speed for eight portions of extended address space within the area of I/O
space from 08FFFFFF to 0FFFFFFF. (Types A and C only.)
E
expansion card area access speed
bit[7] (0F00 0000..0FFF FFFF)
Write
0
1
Type A
Type C
bit[0] (0800 0000..08FF FFFF)
0
1
Type A
Type C
Read
read back above values
June 1997
95
ADVANCE DATA BOOK v2.0
MEMORY AND I/O PROGRAMMERS’ MODEL
CIRRUS [ CIRRUS LOGIC ]
