CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.30 IRQRQD (0x74) — IRQ D Interrupts Request
7
6
5
4
3
2
1
0
X X X 2 1 A T R
2
nEVENT2, active-low wakeup event 2
nEVENT1, active-low wakeup event 1
A-to-D, active-high
1
A
T
mouse transmit active-high
mouse receive active-high
ignored
R
Write
Read
request, status bitwise AND’ed with mask
10.3.31 IRQMSKD (0x78) — IRQ D Interrupts Mask
7
6
5
4
3
2
1
0
X X X 2 1 A T R
2
nEVENT2, active-low wakeup event 2
nEVENT1, active-low wakeup event 1
A-to-D, active-high
1
A
T
mouse transmit active-high
R
mouse receive active-high
Write
set mask for each interrupt source
0
1
do not form part of nIRQ
form part of nIRQ
Read
Reset
value set by write
set all ‘0’ (none affect nIRQ)
92
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
