CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.33 REFCR (0x8C) — Refresh Period
7
6
5
4
3
2
1
0
X X X X R R R R
This register programs the DRAM refresh period. It is set to the fastest available rate during reset, as
refresh continues during reset to ensure that the requirements of DRAM specification can be fully met.
R
refresh period
Write
bit[3:0]
0000 refresh off
0001 16 µs
0010 32 µs
0100 64 µs
1000 128 µs
all others are undefined
Read
Reset
return the above values
set to ‘0001’ (fastest available refresh rate)
10.3.34 ID0 (0x94) — Chip ID Number (Low Byte)
7
6
5
4
3
2
1
0
0 1 1 1 1 1 0
0
The ID registers and the version register read back the CL-PS7500FE ID and version numbers. These
registers are read-only and must not be written to, as they are used to set the CL-PS7500FE into special
modes during production test.
Write
Read
do not write to this location
low byte of chip ID: 0x7C
10.3.35 ID1 (0x98) — Chip ID Number (High Byte)
7
6
5
4
3
2
1
0
1 0 1 0 1 0 1 0
Write
Read
do not write to this location
high byte of chip ID: 0xAA
10.3.36 VERSION (0x9C) — Chip Version Number
Write
Read
ignored
chip version number byte
10.3.37 MSEDAT (0xA8) — Mouse Data
The Mouse Data and Control registers are identical to the keyboard data and control registers, and are
written to and read from in exactly the same way.
94
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
