CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.43 SELFREF (0xD4) — DRAM Self-Refresh Control
7
6
5
4
3
2
1
0
C C C C R R R R
Direct software control of the external nRAS[3:0] and nCAS[3:0] lines is provided by this register. This is
intended for use with self-refresh DRAMs, so that before the CL-PS7500FE is forced into STOP mode,
the banks of DRAM can be set into a self-refresh state from software by forcing the nRAS and nCAS lines
as specified in the DRAM data sheet.
C
force all nCAS low
force all nRAS low
bits[7:4]
R
Write
0
1
normal
force to ‘0’
bits[3:0]
0
1
normal
force to ‘0’
Read
Reset
reads above values
set bits to ‘0’ (normal)
10.3.44 ATODICR (0xE0) — A-to-D Interrupt Control
7
6
5
4
3
2
1
0
S F A C 4 3 2 1
The A-to-D convertor interface is designed so that various combination of interrupts from the channels
can be used to generate an interrupt request in the IRQD interrupt request register. Note that the logical
OR of all four basic enables powers up the comparators. As the comparators consume static current, they
must be powered down by disabling all the A-to-D channels using this register before STOP mode is
entered.
1
channel 1 interrupt enable
2
channel 2 interrupt enable
3
channel 3 interrupt enable
4
channel 4 interrupt enable
C
any combination of channels generates nIRQ
only all channels enabled generates nIRQ
first pair enabled generates nIRQ
second pair enabled generates nIRQ
bit[7:0]
A
F
S
Write
0
1
disabled
enabled
Read
Reset
return above values
reset to 0x0F
NOTE: The OR of bit[3:0] powers up all the comparators. Thus they reset to the powered-up state.
June 1997
97
ADVANCE DATA BOOK v2.0
MEMORY AND I/O PROGRAMMERS’ MODEL
CIRRUS [ CIRRUS LOGIC ]
