CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.47 ATODCNT1 (0xEC) — A-to-D Counter 1
Write
Read
ignored
returns 16-bit counter value
10.3.48 ATODCNT2 (0xF0) — A-to-D Counter 2
Write
Read
ignored
returns 16-bit counter value
10.3.49 ATODCNT3 (0xF4) — A-to-D Counter 3
Write
Read
ignored
returns 16-bit counter value
10.3.50 ATODCNT4 (0xF8) — A-to-D Counter 4
Write
Read
ignored
returns 16-bit counter value
10.3.51 SDCURA (0x180) — Sound DMA Current A
31
29 28
12 11
4
3
0
P P P P P P P P P P P P P P P P P F F F F F F F F
X
X
X
0 0 0 0
The operation of the sound DMA channel is described in Chapter 9. The sound current registers are pro-
grammed with a page address and the offset within that page to describe the precise location of the first
DMA fetch. The value in the register is then increased by 16 following each DMA access.
P
page[16:0]
F
offset[11:0]
Write
bits[31:29] unused
bits[28:12] page of next DMA fetch
bits[11:4] offset within page of next DMA fetch
bits[3:0] ignored
Read
bits[31:29] undefined
bits[28:4] current DMA fetch location
bits[3:0] always ‘0’
June 1997
99
ADVANCE DATA BOOK v2.0
MEMORY AND I/O PROGRAMMERS’ MODEL
CIRRUS [ CIRRUS LOGIC ]
