CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.52 SDENDA (0x184) — Sound DMA End A
31
30 29
12 11
4
3
0
S
L
X X X X X X X X X X X X X X X X X X E E E E E E E E 0 0 0 0
Program this register with the offset within the page of the final qword. Bit 30 should always be pro-
grammed to ‘0’, unless the channel is being initialized for a single transfer – when it must be programmed
high.
S
stop bit
L
last bit
E
end[11:0]
bit[31] stop bit:
Write
0
1
do not stop after reaching End
stop after reaching End
bit[30] last bit
0
1
not last transfer
last qword transfer
bits[11:4] last DMA location within page selected
bits[3:0] ignored
Read
bits[31:30, 11:4] value written
bits[3:0] always ‘0’
10.3.53 SDCURB (0x188) — Sound DMA Current B
31
29 28
12 11
4
3
0
P P P P P P P P P P P P P P P P P F F F F F F F F
X
X
X
0 0 0 0
The B pair of registers for the sound DMA channel are used in exactly the same way as the A pair, to
enable DMA to continue from the page addressed by one set of registers while the other set are being
reprogrammed.
P
page[16:0]
F
offset[11:0]
Write
bits[31:29] unused
bits[28:12] page of next DMA fetch
bits[11:4] offset within page of next DMA fetch
bits[3:0] ignored
Read
bits[31:29] undefined
bits[28:4] current DMA fetch location
bits[3:0] always ‘0’
100
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
