CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.55 SDCR (0x190) — Sound DMA Control
7
6
5
4
3
2
1
0
C 0 E 1 0 0 0 0
This register controls the sound DMA channel and its state machine. Only two bits can be written to:
¥
¥
bit 7 clears the state machine into a state where it has overrun and is requesting an interrupt.
bit 6 enables the sound DMA channel.
C
clear
E
enable
Write
bit[7] clear
0
1
do not clear state machine
clear state machine. Self clearing
bit[6] not used
bit[5] enable
0
1
disabled
enabled
bits[4:0] not used
bit[7] always reads ‘0’
bit[6] always reads ‘0’
bit[5] enable
Read
0
1
disabled
enabled
bits[4:0] read as ‘10000’ (binary), indicating a qword transfer
enable set to ‘0’
Reset
10.3.56 SDST (0x194) — Sound DMA Status
7
6
5
4
3
2
1
0
X X X X X O I W
The sound DMA status register shows the status of the state machine that controls sound DMA accesses.
It cannot be written to.
O
overrun
I
interrupt request
A or B buffer indication
ignored
W
Write
Read
bits[7:3] unused
bits[2:0] direct state machine state
set to ‘110’ (binary)
Reset
102
June 1997
MEMORY AND I/O PROGRAMMERS’ MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
