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CS51313GDR16 参数 Datasheet PDF下载

CS51313GDR16图片预览
型号: CS51313GDR16
PDF下载: 下载PDF文件 查看货源
内容描述: CPU同步降压控制器能够实现多线性稳压器 [Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators]
分类和应用: 稳压器控制器
文件页数/大小: 20 页 / 249 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Application Information: continued  
where  
I
where  
RMS(H) = maximum switching MOSFET RMS current;  
P
RMSL = lower MOSFET conduction losses;  
IL(PEAK) = inductor peak current;  
IOUT = load current;  
D = Duty Cycle;  
RDS(ON) = lower FET drain-to-source on-resistance.  
IL(VALLEY) = inductor valley current;  
D = Duty Cycle.  
Once the RMS current through the switch is known, the  
switching MOSFET conduction losses can be calculated:  
The synchronous MOSFET has no switching losses, except  
for losses in the internal body diode, because it turns on  
into near zero voltage conditions. The MOSFET body  
diode will conduct during the non-overlap time and the  
resulting power dissipation (neglecting reverse recovery  
losses) can be calculated as follows:  
P
RMS(H) = IRMS(H)2 × RDS(ON)  
where  
PRMS(H) = switching MOSFET conduction losses;  
IRMS(H) = maximum switching MOSFET RMS current;  
PSWL = VSD × ILOAD × non-overlap time × FSW,  
R
DS(ON) = FET drain-to-source on-resistance  
where  
SWL = lower FET switching losses;  
VSD = lower FET source-to-drain voltage;  
ILOAD = load current  
The upper MOSFET switching losses are caused during  
MOSFET switch-on and switch-off and can be determined  
by using the following formula:  
P
Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-  
to-GATE(L) delay (from CS51313 data sheet Electrical  
Characteristics section);  
PSWH = PSWH(ON) + PSWH(OFF)  
VIN × IOUT × (tRISE + tFALL)  
F
SW = switching frequency.  
=
,
6T  
The total power dissipation in the synchronous (lower)  
MOSFET can then be calculated as:  
where  
PSWH(ON) = upper MOSFET switch-on losses;  
PSWH(OFF) = upper MOSFET switch-off losses;  
PLFET(TOTAL) = PRMSL + PSWL  
,
VIN = input voltage;  
where  
IOUT = load current;  
PLFET(TOTAL) = Synchronous (lower) FET total losses;  
PRMSL = Switch Conduction Losses;  
PSWL = Switching losses.  
Once the total power dissipation in the synchronous FET is  
known the maximum FET switch junction temperature can  
be calculated:  
tRISE = MOSFET rise time (from FET manufacturer’s  
switching characteristics performance curve);  
tFALL = MOSFET fall time (from FET manufacturer’s  
switching characteristics performance curve);  
T = 1/FSW = period.  
The total power dissipation in the switching MOSFET can  
then be calculated as:  
TJ = TA + [PLFET(TOTAL) × RθJA],  
PHFET(TOTAL) = PRMSH + PSWH(ON) + PSWH(OFF)  
,
where  
TJ = MOSFET junction temperature;  
where  
T
A = ambient temperature;  
PHFET(TOTAL) = total switching (upper) MOSFET losses;  
PRMSH = upper MOSFET switch conduction Losses;  
PSWH(ON) = upper MOSFET switch-on losses;  
PSWH(OFF) = upper MOSFET switch-off losses.  
PLFET(TOTAL) = total synchronous (lower) FET losses;  
θJA = lower FET junction-to-ambient thermal resistance.  
R
Step 8: Control IC Power Dissipation  
Once the total power dissipation in the switching FET is  
known, the maximum FET switch junction temperature  
can be calculated:  
The power dissipation of the IC varies with the MOSFETs  
used, VCC, and the CS51313 operating frequency. The aver-  
age MOSFET gate charge current typically dominates the  
control IC power dissipation.  
TJ = TA + [PHFET(TOTAL) × RθJA],  
The IC power dissipation is determined by the formula:  
where  
TJ = FET junction temperature;  
TA = ambient temperature;  
PHFET(TOTAL) = total switching (upper) FET losses;  
PCONTROLIC = ICCVCC + PGATE(H) + PGATE(L)  
,
where  
R
θJA = upper FET junction-to-ambient thermal resistance  
PCONTROLIC = control IC power dissipation;  
ICC = IC quiescent supply current;  
VCC = IC supply voltage;  
Step 7b: Selection of the synchronous (lower) FET  
PGATE(H) = upper MOSFET gate driver (IC) losses;  
PGATE(L) = lower MOSFET gate driver (IC) losses.  
The upper (switching) MOSFET gate driver (IC) losses are:  
The switch conduction losses for the lower FET can be cal-  
culated as follows:  
PRMSL = IRMS2 × RDS(ON) = [IOUT  
× ,  
(1 D)]2 × RDS(ON)  
PGATE(H) = QGATE(H) × FSW × VGATE(H)  
,
15  
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