50S116T
SDRAM
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power-up sequence is further described in the "Functional Description" section.
6. AC test conditions.
PARAMETER
Output Reference Level
CONDITIONS
1.4V/1.4V
See diagram below
2.4V/0.4V
2 nS
Output Load
Input Signal Levels
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
1.4V
1.4 V
50 ohms
30pF
output
Z = 50 ohms
AC TEST LOAD
7. Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 16 of 42
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CERAMATE [ CERAMATE TECHNICAL ]
