PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 1 (29) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
UG1
UG1
UG1
UG1
UG1
UG1
UG1
UG1
0
7
6
5
4
3
2
1
Reg
29
Bit
Name
UG1
Description
7-0
U gain, 8 lsbs. Bottom 8 bits of the U gain
7-0
lsb = 1/256
Buffered register set 1 (2A) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
VG1
VG1
VG1
VG1
VG1
VG1
VG1
VG1
0
7
6
5
4
3
2
1
Reg
2A
Bit
Name
VG1
Description
7-0
V gain, 8 lsbs. Bottom 8 bits of the V gain
7-0
lsb = 1/256
Buffered register set 1 (2B) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
YG1
UG1
UG1
UG1
Reserved
VG1
VG1
9
8
10
9
8
9
8
Reg
Bit
Name
Description
2B
7-6
YG1
Y gain, 2 msbs. Top 2 bits of the Y gain
9-8
msb = 2
2B
5-3
UG1
U gain, 3 msbs. Top 3 bits of the U gain.
10-8
msb = 4
2B
2B
2
Reserved
VG1
reserved, set to zero
1-0
V gain, 2 msbs. Top 2 bits of the V gain
9-8
msb = 2
Buffered register set 1 (2C) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
YOFF1
0
7
6
5
4
3
2
1
Reg
2C
Bit
7-0
Name
Description
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
YOFF1
7-0
REV. 1.0.0 2/4/03
31
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
