TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Format Control (26)
7
6
5
4
3
2
1
0
Reserved
LDVIO
OPCKS
DPCEN
DPC
Reg
26
Bit
7-6
5
Name
Description
Reserved, set to zero.
Reserved
LDVIO
26
LDV clock select. LDV is an output when LOW and an input when HIGH
26
4
OPCKS
Output clock select. The output data are clocked by the CLOCK pin when
LOW and by the LDV pin when HIGH.
26
26
3
DPCEN
DPC
DPC enable. When HIGH on the TMC22153A, the Decoder Product Code is
enabled: a value written into DPC determines the decoder product emulated
by the TMC22153A. In all other versions of the decoder, DPC is read-only,
and returns the code of the particular encoder version installed.
2-0
Decoder product code
DPC
000
Function
Reserved
001
010
011
100
101
110
111
TMC22051A
TMC22052A
TMC22053A
Reserved
TMC22151A
TMC22152A
TMC22153A
Read/Write in the TMC22153A only. Read-only in all other devices.
Buffered register set 1 (27) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SG1
SG1
SG1
SG1
SG1
SG1
SG1
SG1
0
7
6
5
4
3
2
1
Reg
27
Bit
Name
SG1
Description
7-0
Msync gain, 8 lsbs. Bottom 8 bits of the mixed sync scalar
7-0
lsb = 1/256
Buffered register set 1 (28) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
YG1
YG1
YG1
YG1
YG1
YG1
YG1
0
7
6
5
4
3
2
1
Reg
28
Bit
Name
YG1
Description
7-0
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
7-0
lsb = 1/256
30
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
