PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Video Measurement (30)
7
6
5
4
3
2
1
0
Reserved
LGF
LGEN
LGEXT
RESERVED
PGG
PGEN
PGEXT
Reg
Bit
Name
Reserved
LGF
Description
Reserved, set to zero.
30
30
7
6
Line grab flag. Set HIGH when the decoder has grabbed a line, and must be
reset LOW before another line can be grabbed.
30
5
LGEN
Line grab enable. When HIGH, the line grabber is used to freeze the
contents of the line store, at the programmed line and field count. The phase
and frequency of the frozen line are also stored from the DRS, and are
continually used to reset the DDS, once per line, until LGF is set LOW. When
LGEN is LOW, the line freeze is disabled, the internal loops operate normally,
and the line grab signal is used only to gate the pixel grab.
30
4
LGEXT
Ext line grab enable. The SET pin is used to produce the line grabber pulse
when HIGH and the internal line decode is used when LGEXT is LOW.
30
30
3
2
Reserved
PGG
Reserved, set to zero.
Pixel grab gate. When HIGH the pixel grab is gated by the field and line grab
signals to enable one pixel per four fields in NTSC and 8 field in PAL to be
grabbed. This function is disabled if PGEN is set LOW.
30
30
1
0
PGEN
Pixel grab enable. When HIGH the 10 bit G/Y, B/U, and R/V data, and the
mixed sync and luma data after the comb filter, and the demodulated (B-Y)
and (R-Y) color difference signals are grabbed once every line at the
programmed pixel grab number. When LOW the contents of the pixel grab
registers are held and the pixel grab pulse is ignored.
PGEXT
Ext pixel grab enable. The SET pin is used to produce the pixel grab pulse
when HIGH and the internal pixel decode is used when PGEXT is LOW.
Video Measurement (31)
7
6
5
4
3
2
1
0
PG
PG
PG
PG
PG
PG
PG
PG
0
7
6
5
4
3
2
1
Reg
31
Bit
Name
PG
Description
Pixel grab, 8 lsbs. Bottom 8 bits of the pixel grab.
7-0
7-0
Video Measurement (32)
7
6
5
4
3
2
1
0
LG
LG
LG
LG
LG
LG
LG
LG
0
7
6
5
4
3
2
1
Reg
32
Bit
Name
LG
Description
Line grab, 8 lsbs. Bottom 8 bits of the line grab.
7-0
7-0
REV. 1.0.0 2/4/03
33
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
