TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 1 (2D) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
Reserved
YOFF1
SG1
SG1
8
8
9
Reg
2D
Bit
7-3
2
Name
Description
Reserved
Reserved, set to zero.
2D
YOFF1
Y offset, msb. msb of YOFF
8
2D
1-0
SG1
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar
9,8
msb = 2
Buffered register set 1 (2E) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
0
VAXISO
6
5
4
3
2
1
Reg
2E
Bit
7-1
0
Name
Description
SYSPH1
VAXIS1
7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset
V axis flip. Flips the sign of the V axis when HIGH.
6-0
2E
Buffered register set 1 (2F) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
SYSPH1
7
14
13
12
11
10
9
8
Reg
Bit
Name
Description
8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
2F
7-0
SYSPH1
14-7
32
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
