PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 0 (1C) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
YOFF0
0
7
6
5
4
3
2
1
Reg
1C
Bit
7-0
Name
Description
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
YOFF0
7-0
Buffered register set 0 (1D) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
Reserved
YOFF0
SG0
SG0
8
8
9
Reg
1D
Bit
7-3
2
Name
Description
Reserved
Reserved, set to zero.
1D
YOFF0
Y offset, msb. msb of YOFF
8
1D
1-0
SG0
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar.
9-8
msb = 2
Buffered register set 0 (1E) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
0
VAXIS0
6
5
4
3
2
1
Reg
1E
Bit
7-1
0
Name
Description
SYSPH0
VAXIS0
7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset
V axis flip. Flips the sign of the V axis when HIGH.
6-0
1E
Buffered register set 0 (1F) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
SYSPH0
7
14
13
12
11
10
9
8
Reg
Bit
Name
Description
8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
1F
7-0
SYSPH0
14-7
Normalized Subcarrier Frequency (20)
7
6
5
4
3
2
1
0
FSC
FSC
FSC
FSC
0
Reserved
3
2
1
Reg
Bit
7-4
3-0
Name
FSC
Description
20
20
Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED
3-0
Reserved
Reserved, set to zero.
REV. 1.0.0 2/4/03
27
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
